2. 技术支持
  3. AR# 6927:
  4. AR# 69274: LogiCORE IP MIPI D-PHY v3.1, v3.1 (Rev. 1) and v4.0 (Rev. 1) - Why does the ulpsactivenot only assert for one clock period for the MIPI D-PHY RX?

AR# 69274

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LogiCORE IP MIPI D-PHY v3.1, v3.1 (Rev. 1) and v4.0 (Rev. 1) - Why does the ulpsactivenot only assert for one clock period for the MIPI D-PHY RX?

描述

Why does the ulpsactivenot only assert for one clock period for the MIPI D-PHY RX?

According to the MIPI Specification, the ulpsactivenot should remain asserted until the source starts Mark-1.

解决方案

This issue occurs in the Vivado 2017.2 and 2017.4 generated LogiCORE MIPI D-PHY.

This issue is fixed in Vivado 2017.3, and has been fixed in Vivado 2018.1 and later.

  • Vivado 2017.3 - This issue is resolved in the MIPI D-PHY in Vivado 2017.3.
  • Vivado 2017.4 - Users can download the MIPI D-PHY from (Xilinx Answer 70530) to work around this issue.
  • Vivado 2018.1 - This issue is resolved in the MIPI D-PHY in Vivado 2018.1 and later.

It is recommended to update to the latest version of the IP.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54550 LogiCORE IP MIPI D-PHY - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions N/A N/A
70530 2017.4 LogiCORE IP MIPI D-PHY v4.0 (rev.1) - Patch Updates for the MIPI D-PHY LogiCORE IP v4.0 (rev.1) N/A N/A
AR# 69274
日期 04/24/2018
状态 Active
Type 综合文章
器件 More Less
IP
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