This answer record contains patch updates for the LogiCORE IP MIPI CSI-2 Transmitter Subsystem in 2017.1.
This patch fixes the following issue in the LogiCORE IP MIPI CSI-2 Transmitter Subsystem v1.0 (Rev. 2) in the Vivado 2017.1 design tools.
| (Xilinx Answer 69250) | Why is the MIPI Transmitter Clock/Data relationship not center-aligned for some line-rate configurations? |
See the individual Answer Record for details on which release the issue is fixed in.
This patch is only available for Vivado 2017.1.
This patch will no longer be required for Vivado 2017.2 or later.
Patch Installation:
Install the patch as per the instructions in the included README.txt file to resolve this issue.
| 文件名 | 文件大小 | File Type |
|---|---|---|
| AR69173_vivado_2017_1_preliminary_rev1.zip | 7 MB | ZIP |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 67896 | MIPI CSI-2 Transmitter Subsystem - Release Notes and Known Issues for the Vivado 2016.3 tool and later versions | N/A | N/A |
| 54550 | LogiCORE IP MIPI D-PHY - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions | N/A | N/A |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 69250 | LogiCORE IP MIPI CSI-2 Transmitter Subsystem v1.0 (Rev. 2) - Why is the MIPI Transmitter Clock/Data relationship not center-aligned for some line-rate configurations? | N/A | N/A |