AR# 66780

描述

The Xilinx AXI SmartConnect LogiCORE IP core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices.

This Answer Record contains known issues for the core.

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解决方案

2020.1 and Later Versions Limitations

• Exclusive access transactions (using the AXI ARLOCK/AWLOCK signal) are supported beginning in the 2020.1 release with limitations.
  
  • SmartConnect propagates the AxLOCK signal from the Slave Interface (SI) to the Master Interface (MI) without modification.
  • SmartConnect does not propagate the AXI ID signal nor does it manage the semaphore.
  • The endpoint slave can manage exclusive access based on bits propagated in the AxUSER field. The AxUSER bits should uniquely identify the master requesting the lock.

2019.2 Limitations

• The SmartConnect IP is only available in Vivado IP Integrator
• There are no transaction acceptance limits enforced at this time. Transactions received on the SI are issued to the MI up to the point at which internal command queues become filled, at which time further commands are stalled until buffer space becomes available.
• Endpoint MI multi-threading is not supported. No AxID bits are propagated to the Master Interface.
• Exclusive access transactions (using the AXI ARLOCK/AWLOCK signal) are not supported at this time. Any transaction received with ARLOCK/AWLOCK asserted will be propagated to the MI with ARLOCK/AWLOCK de-asserted.
  
  • SmartConnect does not preserve ID bits and transaction characteristics necessary for Exclusive Accesses
• SmartConnect supports a limited area-optimized mode. If all of MI interfaces of the SmartConnect are directly connected to 32-bit AXI4-Lite endpoint slaves, area optimization is available. 
• Direct connection means that the endpoint slave is connected directly to the SmartConnect Master Interface (MI). It is not connected through a cascaded SmartConnect.
• For all other configurations, continue to use AXI Interconnect V2.1 in area strategy mode for minimal area applications.
• Only round-robin arbitration is supported
• SmartConnect supports 1x1 configurations to perform in-line AXI conversion or buffering functions, such as data-width conversion or protocol conversion with similar Quality of Results to AXI Interconnect V2.1.
• While multiple instances of SmartConnect can be cascaded, it is not recommended to connect SmartConnect to AXI Interconnect V2.x, or vice-versa.
  The only V2.1 AXI coupler IP that is approved to connect to SmartConnect is the AXI Register Slice V2.1.
• SmartConnect uses AXI metadata in IP Integrator in order to optimize itself.
  Area, latency, and timing can be improved if the AXI master emits metadata on its AXI interface.
  For custom logic, this is accomplished during IP packaging:
• The IP uses only INCR burst (HAS_BURST=0)
• The IP does not require sub-size burst support (SUPPORTS_NARROW=0)
• The IP is read-only or write-only (READ_WRITE_MODE)
• The relationship between NUM_ID and NUM_THREADS is understood.
  
  • If the metadata asks for a NUM_THREADS than available based on NUM_ID, SmartConnect configures based on NUM_ID.
  • If the metadata asks for fewer NUM_THREADS than available based on NUM_ID, SmartConnect stalls transactions after the NUM_THREADS slots are filled. For example: if NUM_ID is 2 and NUM_THREADS is 2 and three writes come in with AWID = 2'b00, AWID = 2'b01 and AWID = 2'b10. Writes 2'b00 and 2'b01 occupy the 2 NUM_THREADS slots. The third write with AWID = 2'b10 will stall until one of the first two writes completes.

The following table provides known issues.

Note: The "Version Found" column lists the version where the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

2017.1 to 2019.1 Limitations and Known Issues

• The SmartConnect IP is only available in Vivado IP Integrator
• There are no transaction acceptance limits enforced at this time. Transactions received on the SI are issued to the MI up to the point at which internal command queues become filled, at which time further commands are stalled until buffer space becomes available.
• Exclusive access transactions (using the AXI ARLOCK/AWLOCK signal) are not supported at this time. Any transaction received with ARLOCK/AWLOCK asserted will be propagated to the MI with ARLOCK/AWLOCK de-asserted.
• Clock-enable (aclken) inputs are not supported at this time.
• No area-optimized mode is supported by SmartConnect at this time. Continue to use axi_interconnect_v2_1 in area strategy mode for minimal area applications and for all pure AXI4-Lite solutions.
• SmartConnect does not preserve ID bits and transaction characteristics necessary for Exclusive Accesses
• Only round-robin arbitration is supported
• Endpoint MI multi-threading is not supported. Endpoint AXI slaves connected to SmartConnect will receive a fixed ID
• It is not recommended to use SmartConnect in a 1x1 configuration to perform in-line AXI conversion or buffering functions, such as data-width conversion or protocol conversion.
  Continue to use the appropriate V2.1 AXI coupler IP for such in-line conversions.
• While multiple instances of SmartConnect can be cascaded, it is not recommended to connect SmartConnect to AXI Interconnect V2.x, or vice-versa.
  The only V2.1 AXI coupler IP that is approved to connect to SmartConnect is the AXI Register Slice V2.1.
• SmartConnect uses AXI Meta data in IP Integrator in order to optimize itself.
  Area, latency, and timing can be improved if the AXI master emits metadata on its AXI interface to indicate.
  For custom logic, this is accomplished during IP packaging:
• The IP uses only INCR burst (HAS_BURST=0)
• The IP does not require sub-size burst support (SUPPORTS_NARROW=0)
• The IP is read-only or write-only (READ_WRITE_MODE)
• The max burst length of the IP is known (MAX_BURST_LENGTH)

2016.1/2016.2 Beta and 2016.3/2016.4 Preproduction Users

• Users must move to the 2017.1 and later release of SmartConnect.
  The Beta/Pre-production versions are no longer supported and are not backward compatible.

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