AR# 57835

描述

Version Found: v1.07a
Version Resolved and other Known Issues: See (Xilinx Answer 44969).

Root Port receives Slave Error (slverr) on the AXI bus during enumeration on non-connected busses or ports which causes processor to hang.

解决方案

During enumeration (device discovery), the Root Complex will try to read all possible busses or ports even when there is no device connected at those locations. When there is no response (unconnected port / bus), it will result in Unsupported Request (UR) per the PCIe specification.

The current AXI Bridge to PCI Express core (v1.08a and earlier) will return the slave error on the AXI bus when Unsupported Request (UR) is received on the PCIe bus during enumeration.

The proper behavior should be to return an OKAY response on the AXI bus because this is intended behavior during enumeration (device discovery) rather than an error.
The core will be fixed in the next release. For the current core release, a patch is attached at the end of this answer record.

1. Upgrade the AXI Bridge for PCIe core to v1.08a released in ISE 14.6 tool.
2. Make the AXI Bridge for PCIe core local by right-clicking the core, then choose Make this IP local within XPS tool.
3. Navigate to the project_directory/pcores/axi_pcie_v1_08_a/hdl/verilog and replace the core_name_a_axi_enhanced_cfg_slave.v file with the attached file in this answer record.
4. Within XPS tool, select Project -> Clean All Generated Files to remove any implemented design.
5. Re-run Synthesis and Implementation.

Note: "Version Found" refers to the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
10/24/2013 - Initial release

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