解决方案
Kintex-7 FPGA Connectivity Kit TRD v1.0 for ISE 14.1 with CES Silicon
In order to set the environment variables, namely XILINX and XILINX_PLANAHEAD, it is required that settings32.sh or settings64.sh be sourced from the ISE installation folder, OR invoke the ISE Design Suite Command Prompt on Windows through the following path in Start menu --> Xilinx ISE Design Suite 14.1 --> Accessories.
CE requirements applicable to Xilinx Evaluation Kits dictate certain PC chassis requirements for PCIe operation; see (Xilinx Answer 50596) for more information.
- Silicon
- The kit ships with Rev E KC705 board with GES silicon. Refer to the XC7K325T ES Errata for any further information.
- IP Cores
- 7 Series PCIe (pcie_x8gen2_axi_st_ip) core: v1.4. On certain machines, it is seen that when changing PCIe link width, PCIe link speed (if at 2.5 Gb/s) automatically comes up to 5 Gb/s.
- 7 Series MIG (mig_axi_mm): v1.5
- AXI Interconnect (axi_interconnect_4m_1s): v1.06a
- AXI4Lite Interconnect (XPS generated): v1.06a
- Ten Gigabit Ethernet MAC (ten_gig_eth_mac_axi_st_ip): v11.3
- Ten Gigabit PCS-PMA (ten_gig_eth_pcs_pma_ip): v2.2. Custom modified for use in the TRD. Refer to (Xilinx Answer 50557) for more information.
- GT Wizard for 10GBASE-R Wrapper: v1.4
- FIFO Generator: v9.1
- PCIe does not link up on Z77 (Ivy Bridge) platform. Refer to (Xilinx Answer 52655) for more information.
- No clock output on TXOUTCLK at cold temperatures. Refer to Design Advisory (Xilinx Answer 53740) for more information.
- Targeted Reference Design
- Graphical user interface may not show power number plots. Refer to (Xilinx Answer 50558) for more information.
- For testing the USE_DIFF_QUAD mode in hardware, as suggested in Chapter 5 of the User Guide; note that the polarity reversal on the SFP+ socket on the KC705 (Rev E) is taken care of in the 'ip_cores/xphy_gt_wrapper/gtwizard_10gbaser_diff_quad_gt.v' file.
- Unzipping the k7_connectivity_trd_v1_0.zip file in Windows and copying over the unzipped folder to Linux leaves some files without having execution permission. The user has to manually run 'chmod +x <file name>' on a terminal to make the files executable.
- TRD by default uses the evaluation version of the DMA IP which times out after 12 hours. A DMA full netlist is shipped along with the TRD which needs a DMA full license. Users can purhcase a DMA full license from NorthWest Logic.
Once full license is obtained, depending on the flow being used (script based or PlanAhead) modify the respective scripts to use the DMA netlist from 'ip_cores/dma/netlist/full' folder instead of 'ip_cores/dma/netlist/eval'.
This requires path change and search directory path change in the scripts.
- Tools
- TRD uses ISE Design Suite 14.1 (Logic or System or Embedded Edition)
- TRD simulated using Modelsim v10.1a
Kintex-7 FPGA Connectivity Kit TRD v1.1 for ISE 14.2 with CES Silicon
In order to set the environment variables, namely XILINX and XILINX_PLANAHEAD, it is required that settings32.sh or settings64.sh be sourced from the ISE installation folder, OR invoke the ISE Design Suite Command Prompt on Windows through the following path in Start menu --> Xilinx ISE Design Suite 14.2 --> Accessories.
CE requirements applicable to Xilinx Evaluation Kits dictate certain PC chassis requirements for PCIe operation, see (Xilinx Answer 50596) for more information.
- Silicon
- The kit ships with Rev E KC705 board with GES silicon. Refer to the XC7K325T ES Errata for any further information.
- IP Cores
- 7 Series PCIe (pcie_x8gen2_axi_st_ip) core: v1.6. On certain machines, it is seen that when changing PCIe link width, PCIe link speed (if at 2.5 Gb/s) automatically comes up to 5 Gb/s.
- 7 Series MIG (mig_axi_mm): v1.6
- AXI Interconnect (axi_interconnect_4m_1s): v1.1
- AXI4Lite Interconnect (XPS generated): v1.06a
- Ten Gigabit Ethernet MAC (ten_gig_eth_mac_axi_st_ip): v11.4
- Ten Gigabit PCS-PMA (ten_gig_eth_pcs_pma_ip): v2.2. Custom modified for use in the TRD. Refer to (Xilinx Answer 50557) for more information.
- GT Wizard for 10GBASE-R Wrapper: v1.4
- FIFO Generator: v9.2
- PCIe does not link up on Z77 (Ivy Bridge) platform. Refer to (Xilinx Answer 52655) for more information.
- No clock output on TXOUTCLK at cold temperatures. Refer to Design Advisory (Xilinx Answer 53740) for more information.
- Targeted Reference Design
- Graphical user interface may not show power number plots. Refer to (Xilinx Answer 50558) for more information.
- For testing the USE_DIFF_QUAD mode in hardware, as suggested in Chapter 5 of the User Guide, note that the polarity reversal on the SFP+ socket on the KC705 (Rev E) is taken care of in the 'ip_cores/xphy_gt_wrapper/gtwizard_10gbaser_diff_quad_gt.v' file.
- Unzipping the k7_connectivity_trd_v1_1.zip file in Windows and copying over the unzipped folder to Linux leaves some files without having execution permission. The user has to manually run 'chmod +x <file name>' on a terminal to make the files executable.
- TRD by default uses the evaluation version of the DMA IP which times out after 12 hours. A DMA full netlist is shipped along with the TRD which needs a DMA full license. Users can purchase a DMA full license from NorthWest Logic.
Once full license is obtained, depending on the flow being used (script based or PlanAhead) modify the respective scripts to use the DMA netlist from 'ip_cores/dma/netlist/full' folder instead of 'ip_cores/dma/netlist/eval'.
This requires path change and search directory path change in the scripts.
- Tools
- TRD uses ISE Design Suite 14.2 (Logic or System or Embedded Edition)
- TRD simulated using Modelsim v10.1a
Kintex-7 FPGA Connectivity Kit TRD v1.2 for ISE 14.3 / 2012.3 with Production Silicon
In order to set the environment variables, namely XILINX and XILINX_PLANAHEAD, it is required that settings32.sh or settings64.sh be sourced from the ISE installation folder, OR invoke the ISE Design Suite Command Prompt on Windows through the following path in Start menu --> Xilinx ISE Design Suite 14.3 --> Accessories.
CE requirements applicable to Xilinx Evaluation Kits dictate certain PC chassis requirements for PCIe operation, see (Xilinx Answer 50596) for more information.
- Silicon
- The kit ships with Rev 1.0 KC705 board with Production silicon.
- IP Cores
- 7 Series PCIe (pcie_x8gen2_axi_st_ip) core: v1.7. On certain machines it is seen that when changing PCIe link width, PCIe link speed (if at 2.5 Gb/s) automatically comes up to 5 Gb/s.
- 7 Series MIG (mig_axi_mm): v1.7
- AXI Interconnect (axi_interconnect_4m_1s): v1.1
- AXI Virtual FIFO Controller: v1.1
- AXI4Lite Interconnect (XPS generated): v1.06a
- Ten Gigabit Ethernet MAC (ten_gig_eth_mac_axi_st_ip): v11.5
- Ten Gigabit PCS-PMA (ten_gig_eth_pcs_pma_ip): v2.5. Custom modified for use in the TRD. Refer to (Xilinx Answer 50557) for more information.
- GT Wizard for 10GBASE-R Wrapper: v2.3
- Fifo Generator: v9.3
- PCIe does not link up on Z77 (Ivy Bridge) platform. Refer to (Xilinx Answer 52655) for more information.
- No clock output on TXOUTCLK at cold temperatures. Refer to Design Advisory (Xilinx Answer 53740) for more information.
- Targeted Reference Design
- Graphical user interface may not show power number plots. Refer to (Xilinx Answer 50558) for more information.\
- For testing the USE_DIFF_QUAD mode in hardware, as suggested in Chapter 5 of the User Guide, note that the polarity reversal on the SFP+ socket on the KC705 (Rev E) is taken care of in the 'ip_cores/xphy_gt_wrapper/gtwizard_10gbaser_diff_quad_gt.v' file.
- Unzipping the k7_connectivity_trd_v1_2.zip file in Windows and copying over the unzipped folder to Linux leaves some files without having execution permission. The user has to manually run 'chmod +x <file name>' on a terminal to make the files executable.
- TRD by default uses the evaluation version of the DMA IP which times out after 12 hours. A DMA full netlist is shipped along with the TRD which needs a DMA full license. Users can purchase a DMA full license from NorthWest Logic.
Once full license is obtained, depending on the flow being used (script based or PlanAhead) modify the respective scripts to use the DMA netlist from 'ip_cores/dma/netlist/full' folder instead of 'ip_cores/dma/netlist/eval'.
This requires path change and search directory path change in the scripts.
- Tools
- TRD uses ISE Design Suite 14.3 (Logic or System or Embedded Edition)
- TRD uses Vivado 2012.3
- TRD simulated using Modelsim v10.1a
Kintex-7 FPGA Connectivity Kit TRD v1.3 for Vivado 2012.4 with Production Silicon
In order to set the environment variables, namely XILINX and XILINX_PLANAHEAD, it is required that settings32.sh or settings64.sh be sourced from the ISE installation folder, OR invoke the ISE Design Suite Command Prompt on Windows through the following path in Start menu --> Xilinx ISE Design Suite 14.4 --> Accessories.
CE requirements applicable to Xilinx Evaluation Kits dictate certain PC chassis requirements for PCIe operation, see (Xilinx Answer 50596) for more information.
- Silicon
- The kit ships with Rev 1.0 KC705 board with Production silicon.
- IP Cores
- 7 Series PCIe (pcie_x8gen2_axi_st_ip) core: v1.8. On certain machines it is seen that when changing PCIe link width, PCIe link speed (if at 2.5 Gb/s) automatically comes up to 5 Gb/s.
- 7 Series MIG (mig_axi_mm): v1.8
- AXI Interconnect (axi_interconnect_4m_1s): v1.1
- AXI Virtual FIFO Controller: v1.1
- AXI4Lite Interconnect (XPS generated): v1.06a
- Ten Gigabit Ethernet MAC (ten_gig_eth_mac_axi_st_ip): v11.5
- Ten Gigabit PCS-PMA (ten_gig_eth_pcs_pma_ip): v2.6. Custom modified for use in the TRD. Refer to (Xilinx Answer 50557) for more information.
- GT Wizard for 10GBASE-R Wrapper: v2.3
- FIFO Generator: v9.3
- PCIe does not link up on Z77 (Ivy Bridge) platform. Refer to (Xilinx Answer 52655) for more information.
- No clock output on TXOUTCLK at cold temperatures. Refer to Design Advisory (Xilinx Answer 53740) for more information.
- Targeted Reference Design
- Graphical user interface may not show power number plots. Refer to (Xilinx Answer 50558) for more information.
- For testing the USE_DIFF_QUAD mode in hardware, as suggested in Chapter 5 of the User Guide, note that the polarity reversal on the SFP+ socket on the KC705 (Rev E) is taken care of in the 'ip_cores/xphy_gt_wrapper/grwizard_10gbaser_diff_quad_gt.v' file
- Unzipping the k7_connectivity_trd_v1_3.zip file in Windows and copying over the unzipped folder to Linux leaves some files without having execution permission. The user has to manually run 'chmod +x <file name>' on a terminal to make the files executable.
- TRD by default uses the evaluation version of the DMA IP which times out after 12 hours. A DMA full netlist is shipped along with the TRD which needs a DMA full license. Users can purchase a DMA full license from NorthWest Logic.
Once full license is obtained, depending on the flow being used (script based or PlanAhead) modify the respective scripts to use the DMA netlist from 'ip_cores/dma/netlist/full' folder instead of 'ip_cores/dma/netlist/eval'.
This requires path change and search directory path change in the scripts.
- Tools
- TRD uses Vivado 2012.4
- TRD simulated using Modelsim v10.1a
Kintex-7 FPGA Connectivity Kit TRD v1.4 for Vivado 2013.1 with Production Silicon
In order to set the environment variables, namely XILINX and XILINX_PLANAHEAD, it is required that settings32.sh or settings64.sh be sourced from the ISE installation folder, OR invoke the ISE Design Suite Command Prompt on Windows.
CE requirements applicable to Xilinx Evaluation Kits dictate certain PC chassis requirements for PCIe operation, see (Xilinx Answer 50596) for more information.
- Silicon
- The kit ships with Rev 1.0 KC705 board with Production silicon.
- IP Cores
- 7 Series PCIe (pcie_x8gen2_axi_st_ip) core: v2.0. On certain machines it is seen that when changing PCIe link width, PCIe link speed (if at 2.5 Gb/s) automatically comes up to 5 Gb/s.
- 7 Series MIG (mig_axi_mm): v1.9a
- AXI Interconnect (axi_interconnect_4m_1s): v1.1
- AXI Virtual FIFO Controller: v2.0
- AXI4Lite Interconnect (XPS generated): v1.06a
- Ten Gigabit Ethernet MAC (ten_gig_eth_mac_axi_st_ip): v12.0
- Ten Gigabit PCS-PMA (ten_gig_eth_pcs_pma_ip): v3.0. Custom modified for use in the TRD. Refer to (Xilinx Answer 50557) for more information.
- GT Wizard for 10GBASE-R Wrapper: v2.3
- FIFO Generator: v10.0
- No clock output on TXOUTCLK at cold temperatures. Refer to Design Advisory (Xilinx Answer 53740) for more information.
- DDR3/DDR2 PRBS Calibration results are not applied. Refer to (Xilinx Answer 55912) for more information.
- Targeted Reference Design
- Graphical user interface may not show power number plots. Refer to (Xilinx Answer 50558) for more information.
- For testing the USE_DIFF_QUAD mode in hardware, as suggested in Chapter 5 of the User Guide, note that the polarity reversal on the SFP+ socket on the KC705 (Rev E) is taken care of in the 'ip_cores/xphy_gt_wrapper/grwizard_10gbaser_diff_quad_gt.v' file
- Unzipping the k7_connectivity_trd_v1_4.zip file in Windows and copying over the unzipped folder to Linux leaves some files without having execution permission. The user has to manually run 'chmod +x <file name>' on a terminal to make the files executable.
- TRD by default uses the evaluation version of the DMA IP which times out after 12 hours. A DMA full netlist is shipped along with the TRD which needs a DMA full license. Users can purchase a DMA full license from NorthWest Logic.
Once full license is obtained, depending on the flow being used (script based or PlanAhead) modify the respective scripts to use the DMA netlist from 'ip_cores/dma/netlist/full' folder instead of 'ip_cores/dma/netlist/eval'.
This requires path change and search directory path change in the scripts.
- Tools
- TRD uses Vivado Design Suite 2013.1
- TRD simulated using Modelsim v10.1b