(VC707) PCIe Design Creation (vc707_PCIe_pdf_xtp144_13.4.pdf) page 21 states:
[..]
- Add this line:
NET "emcclk" LOC = AP24| IOSTANDARD = LVCMOS18;
[..]
However, modifying the design to add this extra constraint to the UCF file results in a MAP error during compilation of the design:
ERROR:MapLib:30 - LOC constraint AP24 on emcclk is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
How can I resolve this and compile the design error-free?
This LOC to pin AP24 is a legacy constraint from a previous architecture.
For the VC707, the "emcclk" pin is AP37, not AP24.
The LOC constraint in the UCF file should read:
NET "emcclk" LOC = AP37 |IOSTANDARD = LVCMOS18;
The VC707 PCIe Design Creation PDF has been updated to reflect this correct constraint.
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
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45382 | Virtex-7 FPGA VC707 Evaluation Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
AR# 46963 | |
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日期 | 02/28/2017 |
状态 | Active |
Type | 综合文章 |
器件 | |
Tools | |
Boards & Kits |