2. 技术支持
  3. AR# 46623: AXI Bridge for PCI Express - Using 128-bit Interface (x8 Gen 1 or x4 Gen 2), an array size mismatch occurrs on Completions with Data with status of Completor Abort or Unsupported Request

AR# 46623

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AXI Bridge for PCI Express - Using 128-bit Interface (x8 Gen 1 or x4 Gen 2), an array size mismatch occurrs on Completions with Data with status of Completor Abort or Unsupported Request

描述

Version Found: 1.02.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)

When using the 128-bit interface (x8 Gen 1 or x4 Gen 2), an issue exists in the bridge logic causing an array size mismatch to be exposed, resulting in a simulation run time error and incorrect bits to be set in hardware. This happens only when Completion TLPswith status of either Completer Abort or Unsupported Request are received.

解决方案

It is unusual to receive Completions TLPswith status other than successful completion, so the likelihood of experiencing this issue is low. This issue is fixed in v1.03a, which will be released in ISE 14.1 software.Prior to the ISE 14.1 software release, if this issue is a concern, please open a case with Xilinx support and refer to this answer record.

Revision History
03/05/2012 - Initial Release

NOTE:The "Version Found" columnlists the version in which the problem was firstdiscovered. The problem might also exist in earlier versions, but no specific testing has been performedto verify earlier versions.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
45988 AXI Bridge for PCI Express - 1 DW Write Transactions on the AXI4 Slave interface create malformed TLPs when using a 32-bit AXI data width N/A N/A
AR# 46623
日期 05/20/2012
状态 Active
Type 已知问题
IP
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