Version Found: 1.00.a
Version Resolved and other Known Issues: see (Xilinx Answer 44969)
The AXI Bridge for PCI Express provides an AXI4-lite interface to access the bridge's control registers. When an incoming write transaction is received by the AXI4-lite Control Interface of the bridge, the write response channel responds with a SLVERR if the register is read only.
This is a known issue with the AXI4-lite Control Interface. Although the registers are Read Only, the write response channel should respond with OKAY instead of SLVERR.This issue is resolved in revision v1.01.a of the bridge.
Revision History
11/30/2011 - Initial Release
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 44969 | AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 | N/A | N/A |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 44969 | AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 | N/A | N/A |
| AR# 44976 | |
|---|---|
| 日期 | 12/15/2012 |
| 状态 | Active |
| Type | 综合文章 |
| IP | |