AR# 36950: ISE Design Suite 12.x - ISE Simulator (ISim) Known Issues
AR# 36950
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ISE Design Suite 12.x - ISE Simulator (ISim) Known Issues
描述
This Answer Record contains a list of known and resolved issues for ISE Simulator in ISE Design Suite 12 releases.
解决方案
Known Issues in ISE Design Suite 12.2
(Xilinx Answer 36950) - Wait statement not supported within Fork/Join statements in Verilog testbenches (Xilinx Answer 36214) -ERROR:HDLCompiler:1461 - "testbench.vhd" Line 59: Access type cannot be a formal of mode out (Xilinx Answer 36200) -WARNING:HDLCompiler:746 - RAMB36E1.vhd Line 3202: Range is empty (null range) (Xilinx Answer 33818)- "ERROR: at x ns: Negative wait time (-2147483647 ps) in File "tb_test.vhd"" (Xilinx Answer 33423)- Error "Simulator is abnormally terminated" (Xilinx Answer 33426)- "ERROR:Simulator:904 - Unable to remove previous simulation file" (Xilinx Answer 33429)- "INFO: Simulator is stopped" when performing VCD dump (Xilinx Answer 32357)- "FATAL_ERROR:Simulator:Fuse.cpp:217:1.95 - Failed to compile one of the generated C code..." (Xilinx Answer 33424)- Memory leak when I delete and add signals to wave window (Xilinx Answer 33427)- Unable to view shared access variables in ISim GUI (Xilinx Answer 33428)- Unable to set breakpoints via "Toggle Breakpoint" context menu option
(Xilinx Answer 34577) -Unable to observe output at output buffers (Xilinx Answer 33819)- "ERROR: Target size 3160144 and source size 6 do not match" (Xilinx Answer 33820)- "FATAL_ERROR:Simulator:CompilerAssert.h:40:1.17 - Internal Compiler Error in file ../src/DIDATUtils.cpp" (Xilinx Answer 34567)- Bi-directional signals are not initialized during simulation restart (Xilinx Answer 33551)- "Simulator:778 - Static elaboration of top level Verilog design unit(s) in library work failed" (Xilinx Answer 33425)- Provide the support for global file (defining the compiler directives) as include file in fuse