AR# 34926

描述

The MIG 7 Series andVirtex-6 FPGA DDR3/DDR2 design is divided into three main pieces - User Interface, Controller, and PHY. This Controller is the middle piece of the design and therefore interfaces to both the User Interface and the PHY. On the other side, the controller interfaces to the User Interface through what is called a Native Interface. This is a low latency interface that does not include any FIFOs to organize the commands and data. The Native Interface can then (optionally) interface to the true User Interface where data and commands are stored and organized in FIFOs. Between the Native Interface and the PHY is called the PHY Interface. Through this interface the user bypasses the Memory Controller altogether and can send memory commands and data directly through the PHY interface .

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

For information on the DFI Interface for MIG Virtex-6 FPGA DDR3/DDR2 design, see (Xilinx Answer 34946).

For information on the User and Native Interfaces for the MIG 7 Series and Virtex-6 FPGA DDR3/DDR2 design, see (Xilinx Answer 33698).

For information on the PHY Only Interface for the MIG 7 series FPGA design, see (Xilinx Answer 51204).

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