AR# 34923

描述

This section of the MIG Design Assistant describes the signals and parameters for the Virtex-6 DDR3/DDR2 designs. Below you will find information related to your specific question.

Note: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

• The User Interface signals and their descriptions can be found under the "Core Architecture" -> "User Interface" section in UG406.
• The Native Interface signals and their descriptions can be found under the "Core Architecture" -> "Native Interface" section in UG406.
• The Physical Interface signals and their descriptions can be found under the "Core Architecture" -> "Physical Interface" section in UG406.
• The Configuration Parameters and their descriptions can be found under the "Customizing the Core" sections in UG406.

• For a list of signals and parameters of interest for debugging simulations please check out the "Debugging Virtex-6 FPGA DDR2/DDR3 SDRAM Designs" -> "Simulation Debug" section in UG406.
• The PHY Later Debug Signals and their descriptions can be found under the "Debugging Virtex-6 FPGA DDR2/DDR3 SDRAM Designs"=>"Hardware Debug" -> PHY Layer Debug Port" section in UG406.

Virtex-6 FPGA Memory Interface Solutions User Guide (UG406):
http://www.xilinx.com/support/documentation/ipinterconnect_mig-v6s6.htm

Additional Information
(Xilinx Answer 40462) MIG 7 Series and Virtex-6 DDR2/DDR3 - How are CAS Latency (CL) and CAS Write Latency (CWL - DDR3 only) determined?

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