This section of the MIG Design Assistant will guide you to details on the User Interface for the Virtex-6 and 7 series FPGAs DDR3/DDR2 designs. Please select from the options below to find information related to your specific question.
NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
(Xilinx Answer 34789) - User Interface and Parameter Descriptions
(Xilinx Answer 33698) - Driving the Core Interface (User Interface / Native Interface)
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 51675 | MIG 7 Series Solution Center Design Assistant - Core Functionality | N/A | N/A |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 33698 | MIG 7 系列和 Virtex-6 FPGA DDR2/DDR3 - 如何驱动用户接口？ | N/A | N/A |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 34789 | MIG Virtex-6 and 7 Series DDR2/DDR3 User Interface - Signal and Parameter Descriptions | N/A | N/A |
| 34282 | MIG Design Assistant - Virtex-6 Core Functionality | N/A | N/A |
| 33698 | MIG 7 系列和 Virtex-6 FPGA DDR2/DDR3 - 如何驱动用户接口？ | N/A | N/A |