AR# 34789

描述

This part of the MIG Design Assistant will guide you to information on the User Interface signals and parameters.

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

User Interface

The User Interface to the MIG DDR2/DDR3 core includes all the signals which the user is responsible for driving in order to access the external memory device. All the User Interface signals start with "app_", except for the reset (RST) and clock (clk) inputs.

For a complete list of signals and descriptions, see the DDR2 and DDR3 SDRAM Interface Solution > Core Architecture > User Interface section of the Virtex-6 Memory Interface Solutions User Guide and the 7 Series FPGAs Memory Interface Solutions User Guide.

Core Parameters

The Core Parameters set in the top level of the core HDL are determined by user selections in the MIG GUI. Changes to core parameters should be managed through the MIG GUI by recustomizing the core as needed. For a description of core parameters and list of acceptable values, see the DDR2 and DDR3 SDRAM Interface Solution > Customizing the Core section of the Virtex-6 Memory Interface Solutions User Guide and the 7 Series FPGAs Memory Interface Solutions User Guide.

(Xilinx Answer 34763) - Performing Reads
(Xilinx Answer 34677) - Performing Writes
(Xilinx Answer 35091) - Using the app_rdy signal

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