This answer record contains the Release Notes and Known Issues list for the CORE Generator software and LogiCORE IP Image Noise Reduction.
The following information is listed for each version of the core:
Note: This core has been superseded by the LogiCORE Image Enhancement core (Xilinx Answer 54525) released in Vivado Design Suite 2013.2 and will be removed from the IP catalog as of 2014.1.
As of June 2014, no new licenses will be issues and after June 2015, support will no longer be available.
| (Xilinx Answer 34828) | How do I simulate my Video IP pcore in EDK? |
| (Xilinx Answer 51589) | Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK? |
| (Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
| (Xilinx Answer 50909) | 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow? |
| (Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
| (Xilinx Answer 52215) | Why does my core fail timing with an Critical Warning? |
| (Xilinx Answer 52215) | Why does my core fail timing with an Critical Warning? |
| (Xilinx Answer 51589) | Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK? |
| (Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
| (Xilinx Answer 50909) | 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow? |
| (Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
| (Xilinx Answer 33913) | Why does generation fail when I try to use "noise" for the Component Name? |
| (Xilinx Answer 33872) | "ERROR: sim - An IP generation script exited abnormally. Error found during generation." |
| (Xilinx Answer 35130) | Why do I get the following error when generating with a Design Linking License? ERROR: sim - Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380 - The design contains secured core. |
| (Xilinx Answer 35437) | Why do I see an error saying my core failed to generate on Linux, when there is an uppercase letter in the component name? |
| (Xilinx Answer 46301) | Why does the output image look like it is and overlapping version of the input image? |
| (Xilinx Answer 33913) | Why does generation fail when I try to use "noise" for the Component Name? |
| (Xilinx Answer 33872) | "ERROR: sim - An IP generation script exited abnormally. Error found during generation." |
| (Xilinx Answer 35130) | Why do I get the following error when generating with a Design Linking License? ERROR: sim - Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380 - The design contains secured core. |
| (Xilinx Answer 35437) | Why do I see an error saying my core failed to generate on Linux, when there is an uppercase letter in the component name? |
| (Xilinx Answer 46301) | Why does the output image look like it is and overlapping version of the input image? |
| (Xilinx Answer 33913) | Why does generation fail when I try to use "noise" for the Component Name? |
| (Xilinx Answer 33872) | "ERROR: sim - An IP generation script exited abnormally. Error found during generation." |
| (Xilinx Answer 35130) | Why do I get the following error when generating with a Design Linking License? ERROR: sim - Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380 - The design contains secured core. |
| (Xilinx Answer 35437) | Why do I see an error saying my core failed to generate on Linux, when there is an uppercase letter in the component name? |
| (Xilinx Answer 37987) | Where can I find UG762: Xilinx Streaming Video Interface User Guide? |
| (Xilinx Answer 46301) | Why does the output image look like it is and overlapping version of the input image? |
| AR# 33750 | |
|---|---|
| 日期 | 08/03/2018 |
| 状态 | Archive |
| Type | 版本说明 |
| IP | |