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  3. AR# 32134: LogiCORE IP Defective Pixel Correction - Release Notes and Known Issues

AR# 32134

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LogiCORE IP Defective Pixel Correction - Release Notes and Known Issues

描述

This answer record contains the Release Notes and Known Issues list for the CORE Generator tool and LogiCORE IP Defective Pixel Correction Core.

The following information is listed for each version of the core:

  • New Features
  • Bug Fixes
  • Known Issues


Note: Not recommended for new designs. The core is removed from IP catalog as of 2014.1. Please contact Xylon, our IP partner, for solutions related to defective pixel correction.

解决方案

General LogiCORE IP Defective Pixel Correction Issues

(Xilinx Answer 34828) How do I simulate my Video IP pCore in EDK?

LogiCORE IP Defective Pixel Correction v6.01.a

  • Initial release in ISE 14.3 and Vivado 2012.3 design tools

Supported Devices (ISE)

  • All 7 Series
  • All Virtex-6
  • All Spartan-6

Supported Devices (Vivado)

  • All 7 Series

New Features

  • Fixed clock domain issues with registers in the AXI4-Lite connection

Resolved Issues (ISE)

(Xilinx Answer 51589) Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK?
(Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

Resolved Issues (Vivado)

(Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
(Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

Known Issues (ISE)

(Xilinx Answer 52215) Why does my core fail timing with an Critical Warning?
(Xilinx Answer 58423) Why do I get a rresp=0x2 slave error, when trying to read register address 0x120?

Known Issues (Vivado)

(Xilinx Answer 52215) Why does my core fail timing with an Critical Warning?
(Xilinx Answer 58423) Why do I get a rresp=0x2 slave error, when trying to read register address 0x120?


LogiCORE IP Defective Pixel Correction v6.00.a

  • Initial release in ISE 14.2 and Vivado 2012.2 tools

Supported Devices (ISE)

  • All 7 series
  • All Virtex-6
  • All Spartan-6

Supported Devices (Vivado)

  • All 7 series

New Features

  • Separate clock domains between AXI4-Lite and AXI4-Stream

Bug Fixes

  • N/A

Known Issues (ISE)

(Xilinx Answer 51589) Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK?
(Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

Known Issues (Vivado)

(Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
(Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?


LogiCORE IP Defective Pixel Correction v5.00.a

  • Initial release in ISE 14.1 and Vivado 2012.1 tools

Supported Devices (ISE)

  • Virtex-7
  • Kintex-7
  • Artix-7
  • Zynq-7000
  • Virtex-6
  • Spartan-6

Supported Devices (Vivado)

  • Virtex-7
  • Kintex-7
  • Artix-7
  • Zynq-7000

New Features

  • ISE 14.1 tool support
  • AXI4-Stream data interfaces
  • Optional AXI4-Lite control interface
  • Built-in, optional bypass and test-pattern generator mode
  • Built-in, optional throughput monitors
  • Supports spatial resolutions from 32x32 up to 7680x7680
  • Supports 1080P60 in all supported device families
  • Supports 4kx2k @ 24 Hz in supported high performance devices

Bug Fixes

  • N/A

Known Issues (ISE)

  • N/A

Known Issues (Vivado)

(Xilinx Answer 47450) Why does the Defective Pixel Correction core always use the default values, when using the constant mode in Vivado?
(Xilinx Answer 47451) Why is my design containing the Defective Pixel Correction failing with a multiple driver error when using Vivado Synthesis?


LogiCORE IP Defective Pixel Correction v4.0

  • Initial Release in ISE Design Suite 13.3

Supported Devices

  • Virtex-7
  • Virtex-7 XT (7vx485t)
  • Virtex-7 -2L
  • Kintex-7
  • Kintex-7 -2
  • Virtex-6 XC CXT/LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6 -1L XC LXT/SXT
  • Spartan-6 XC LX/LXT
  • Spartan-6 XA
  • Spartan-6 XQ LX/LXT
  • Spartan-6 -1L XC LX

New Features

  • ISE 13.3 tool support
  • Virtex-7 and Kintex-7 device support
  • AXI4-Lite bus interface support for the EDK Pcore interface

Bug Fixes

  • N/A

Known Issues

  • N/A


LogiCORE IP Defective Pixel Correction v3.0

  • Initial release in ISE Design Suite 13.1

Supported Devices

  • Virtex-6 XC CXT/LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6 -1L XC LXT/SXT
  • Spartan-6 XC LX/LXT
  • Spartan-6 XA
  • Spartan-6 XQ LX/LXT
  • Spartan-6 -1L XC LX
  • Virtex-5 XC LX/LXT/SXT/TXT/FXT
  • Virtex-5 XQ LX/ LXT/SXT/FXT
  • Spartan-3A DSP

New Features

  • New algorithm for detecting and correcting defective pixels
  • New EDK pCore API functions
  • ISE 13.1 tool support

Bug Fixes

(Xilinx Answer 33872) "ERROR:simAn IP generation script exited abnormally. Error found during generation."

Known Issues

(Xilinx Answer 37987) Where can I find UG762: Xilinx Streaming Video Interface User Guide?


LogiCORE IP Defective Pixel Correction v2.0

  • Initial release in ISE Design Suite 12.2

New Features

  • ISE 12.2 tool support
  • Spartan-6 and Virtex-6 device support
  • Linux 32 and 64-bit support
  • XSVI bus interface support for the EDK Pcore interface

Bug Fixes

(Xilinx Answer 35130) Why do I get the following error when generating with a Design Linking License? "ERROR:simError: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380The design contains secured core".

Known Issues

(Xilinx Answer 33872) "ERROR:sim An IP generation script exited abnormally. Error found during generation."
(Xilinx Answer 37987) Where can I find UG762: Xilinx Streaming Video Interface User Guide?


LogiCORE IP Defective Pixel Correction v1.0

  • Initial release in ISE Design Suite 11.1

New Features

  • Programmable thresholds
  • Selectable processor interfaces
    • EDK pCore
    • General Processor
  • Configurable Kerning Bits
  • Configurable 8, 10, and 12-bit input and output
  • Delay match support for up to 3 sync signals
  • ISE 11.1 design tools support

Bug Fixes

  • N/A

Known Issues

(Xilinx Answer 32340) Why does my Image Pipe Video IP core fail to update the netlist when the parameters or the license is changed, but the component name remains constant?
(Xilinx Answer 33581) Why is the output simulation netlist for my design encrypted, and only readable by ISE Simulator?
(Xilinx Answer 33872) "ERROR:sim - An IP generation script exited abnormally. Error found during generation."
(Xilinx Answer 35130) Why do I get the following error when generating with a Design Linking License? "ERROR:sim - Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380 - The design contains secured core."

链接问答记录

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
47451 LogiCORE IP Defective Pixel Correction v5.00.a (Vivado 2012.1) - Why is my design containing the Defective Pixel Correction core failing with a multiple driver error when using Vivado Synthesis? N/A N/A
47450 LogiCORE IP Defective Pixel Correction v5.00.a (Vivado 2012.1) - Why does the Defective Pixel Correction core always use the default values when using the constant mode in Vivado? N/A N/A
33872 LogiCORE IP Image Processing Pipeline Cores - "ERROR:sim - An IP generation script exited abnormally. Error found during generation." or "ERROR:Sim - assertMcrCacheRoot : Temp environment variable set is too long ..." N/A N/A
52215 14.3 / 2012.2 Video IP - Why does my core fail timing with a critical warning? N/A N/A
51589 14.2 / 2012.2 Video IP - Why does the Video IP stop working (producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK? N/A N/A
58423 LogiCORE IP 缺陷像素校正 v6.01.a, v7.0 - 当我尝试读取寄存器地址 0x120时，为什么收到 rresp=0x2 slave 错误？ N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
35130 LogiCORE IP Image Processing Pipeline Cores - The following error is received when generating with a Design Linking License: "ERROR:sim - Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380 - The design contains secured core" N/A N/A
33872 LogiCORE IP Image Processing Pipeline Cores - "ERROR:sim - An IP generation script exited abnormally. Error found during generation." or "ERROR:Sim - assertMcrCacheRoot : Temp environment variable set is too long ..." N/A N/A
33581 LogiCORE Image Processing Pipeline v1.0 - Why is the output simulation netlist for my design encrypted, and only readable by ISE Simulator? N/A N/A
32340 11.1 CORE Generator - Why do my Image Processing Pipe Video IP cores fail to update the netlist when the parameters or the license are changed, but the component name remains constant? N/A N/A
32136 LogiCORE IP Image Processing Pipeline - Release Notes and Known Issues N/A N/A
47450 LogiCORE IP Defective Pixel Correction v5.00.a (Vivado 2012.1) - Why does the Defective Pixel Correction core always use the default values when using the constant mode in Vivado? N/A N/A
AR# 32134
日期 07/17/2018
状态 Archive
Type 版本说明
IP
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