产品描述
The D16550 is a soft Core of Universal Asynchronous Receiver/Transmitter (UART), functionally identical to the TL16C550A. It allows serial transmission in two modes - UART and FIFO. In the FIFO mode, internal FIFOs are activated, allowing 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both, receive and transmit directions. The D16550 performs serial-to-parallel conversion on data characters, received from a peripheral device or a MODEM and parallel-to-serial conversion on data characters, received from the CPU. The CPU can read a complete status of the UART at any time, during the functional operation. Reported status information includes the type and condition of transfer operations performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt). The D16550 includes a programmable baud rate generator, which is capable of dividing the timing reference clock input by divisors of 1 to (216-1) and producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive the receiver logic. Our soft core has a complete MODEM control capability and a processor-interrupt system. What's more important, interrupts can be programmed to user's requirements, minimizing the computing required to handle the communication link.
主要特性与优势
- Static synchronous design and no internal tri-states
- Fully synthesizable
- Full prioritized interrupt system controls
- Line break generation and detection. Internal diagnostic capabilities: Loop-back controls for communications link fault isolation; Break, parity, overrun, framing error simulation
- Complete status reporting capabilities
- Fully programmable serial interface characteristics: 5-, 6-, 7-, or 8-bit characters; Even, odd or no-parity bit generation and detection; 1-, 1 ½-, or 2-stop bit generation; Internal baud generator
- MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD)
- Independent receiver clock input
- 16 bit programmable baud generator
- False start bit detection
- Independently controlled transmit, receive, line status and data set interrupts
- Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
- In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
- In the FIFO mode transmitter and receiver are each buffered with 16 byte FIFO to reduce the number of interrupts presented to the CPU
- Supports RS232 and RS485 standards
- Majority Voting Logic
- Separate configurable BAUD clock line
- Configuration capability
- Software compatible with 16450 and 16550 UARTs
特色技术文档
