Advanced Waveform-Based Kernel Debugging

The C/C++ code is synthesized using High Level Synthesis (HLS) into a Hardware Description Language (HDL) and later mapped onto the FPGA (xclbin). Especially the hardware- centric algorithm programmer will be very familiar with another debugging approach based on waveforms. This waveform-based HDL debugging is best supported by SDAccel™ through the GUI flow during Hardware Emulation.

Note: For most debugging, the HDL model will not need to be analyzed. Waveform debugging is considered an advanced debugging capability.

To run this flow:

Start SDx, and perform the regular setup.
Select Run > Debug Configurations to open the Debug Configurations.
On the Debug Configurations window, select the current debug configuration from the OpenCL® (OCL) list.
On the Main tab, this displays two Kernel Debug Options: Use RTL waveform for kernel debugging and Launch live waveform. Checkmark both, close the configuration window, and a debug session starts automatically.

After the hardware emulation compilation process is complete, the waveform viewer automatically opens. By default, the waveform viewer shows all interface signals and the following debug hierarchy:

• Kernel Data Transfer: This section shows AXI transfers at the OCL masters to the DDR. Data transfers from all compute units funnel through these interfaces.
These interfaces could be a different bit width than the compute units. If so, then the burst lengths would be different (for example, a burst of sixteen 32-bit words at a compute unit would be a burst of one 512- bit word at the OCL master.)

• Kernel <kernel name> <workgroup size> Compute Unit<CU name>

- CU Stalls (%): This section shows a summary of stalls for the entire compute unit (CU). A bus of all lowest-level stall signals is created, and the bus is represented in the waveform as a percentage (%) of those signals that are active at any point in time.
- Loop Pipeline Activity: This section shows the top-level loop pipeline signals for a CU. This section is only populated for flat CUs
- Data Transfers: This section shows the data transfers for all AXI masters on the CU.
- User Functions: This section lists all of the functions within the hierarchy of the CU.
Function: <function name> Function Stalls: This section lists the three stall signals within this function. Loop Pipeline Activity: This section shows the function-level loop pipeline signals for a CU. The number of pipeline regions is dictated by Vivado® HLS and can typically be identified as compute sections of loops Function I/O: This section lists the I/O for the function. These I/O are of protocol -m_axi, ap_fifo, ap_memory, or ap_none.

Note: As with any waveform debugger, additional debug data of internal signals can be added by selecting the instance of interest from the scope menu and the signals of interest from the object menu. Similarly, debug controls such as restart, HDL breakpoints, as well as HDL code lookup and waveform markers are supported.

The waveform debugging process can also enabled through the XOCC/Makefile flow. Use the following instructions to enable it:

Turn on debug code generation during kernel compilation.
```
xocc -g ...
```
Create an sdaccel.ini file in the same directory as the host executable with the contents below:
```
[Emulation]
launch_waveform=batch

[Debug]
profile=true
timeline_trace=true
device_profile=true
```
Execute Hardware Emulation. The hardware transaction data will be collected in the file named <hardware_platform>-<device_id>-<xclbin_name>.wdb file. This file can directly be opened through the SDAccel GUI.

Note: If the launch_waveform option is set to gui in the emulation section: [Emulation] launch_waveform=gui, then a live waveform viewer will be spawned during the execution of the Hardware Emulation.