pragma HLS resource

Description

Specify that a specific library resource (core) is used to implement a variable (array, arithmetic operation or function argument) in the RTL. If the RESOURCE pragma is not specified, Vivado HLS determines the resource to use.

Vivado HLS implements the operations in the code using hardware cores. When multiple cores in the library can implement the operation, you can specify which core to use with the RESOURCE pragma. To generate a list of available cores, use the list_core command.
TIP: The list_core command is used to obtain details on the cores available in the library. The list_core can only be used in the Vivado HLS Tcl command interface, and a Xilinx device must be specified using the set_part command. If a device has not been selected, the list_core command does not have any effect.

For example, to specify which memory element in the library to use to implement an array, use the RESOURCE pragma. This lets you control whether the array is implemented as a single or a dual-port RAM. This usage is important for arrays on the top-level function interface, because the memory type associated with the array determines the ports needed in the RTL.

You can use the latency= option to specify the latency of the core. For block RAMs on the interface, the latency= option allows you to model off-chip, non-standard SRAMs at the interface, for example supporting an SRAM with a latency of 2 or 3. See Arrays on the Interface in the Vivado Design Suite User Guide: High-Level Synthesis (UG902) for more information. For internal operations, the latency= option allows the operation to be implemented using more pipelined stages. These additional pipeline stages can help resolve timing issues during RTL synthesis.
IMPORTANT!: To use the latency= option, the operation must have an available multi-stage core. Vivado HLS provides a multi-stage core for all basic arithmetic operations (add, subtract, multiply and divide), all floating-point operations, and all block RAMs.

For best results, Xilinx recommends that you use -std=c99 for C and -fno-builtin for C and C++. To specify the C compile options, such as -std=c99, use the Tcl command add_files with the -cflags option. Alternatively, use the Edit CFLAGs button in the Project Settings dialog box. See Creating a New Synthesis Project in the Vivado Design Suite User Guide: High-Level Synthesis (UG902).

Syntax

Place the pragma in the C source within the body of the function where the variable is defined. 

#pragma HLS resource variable=<variable> core=<core>\
latency=<int>

Where:

  • variable=<variable>: A required argument that specifies the array, arithmetic operation, or function argument to assign the RESOURCE pragma to.
  • core=<core>: A required argument that specifies the core, as defined in the technology library.
  • latency=<int>: Specifies the latency of the core.

Example 1

In the following example, a 2-stage pipelined multiplier is specified to implement the multiplication for variable c of the function foo. It is left to Vivado HLS which core to use for variable d.

int foo (int a, int b) {
int c, d;
#pragma HLS RESOURCE variable=c latency=2
c = a*b;
d = a*c;
return d;
}

Example 2

In the following example, the variable coeffs[128] is an argument to the top-level function foo_top. This example specifies that coeffs be implemented with core RAM_1P from the library: 

#pragma HLS resource variable=coeffs core=RAM_1P
TIP: The ports created in the RTL to access the values of coeffs are defined in the RAM_1P core.

See Also

  • Vivado Design Suite User Guide: High-Level Synthesis (UG902)