HLS Pragmas

Optimizations in Vivado HLS

In both SDAccel and SDSoC projects, the hardware kernel must be synthesized from the OpenCL, C, or C++ language, into RTL that can be implemented into the programmable logic of a Xilinx device. Vivado HLS synthesizes the RTL from the OpenCL, C, and C++ language descriptions.

Vivado HLS is intended to work with your SDAccel or SDSoC Development Environment project without interaction. However, Vivado HLS also provides pragmas that can be used to optimize the design: reduce latency, improve throughput performance, and reduce area and device resource utilization of the resulting RTL code. These pragmas can be added directly to the source code for the kernel.

IMPORTANT!:

Although the SDSoC environment supports the use of HLS pragmas, it does not support pragmas applied to any argument of the function interface (interface, array partition, or data_pack pragmas). Refer to "Optimizing the Hardware Function" in the SDSoC Environment Optimization Guide (UG1235) for more information.

The Vivado HLS pragmas include the optimization types specified below:

Table 1. Vivado HLS Pragmas by Type
Type	Attributes
Kernel Optimization	pragma HLS allocation pragma HLS clock pragma HLS expression_balance pragma HLS latency pragma HLS reset pragma HLS resource pragma HLS top
Function Inlining	pragma HLS inline pragma HLS function_instantiate
Interface Synthesis	pragma HLS interface pragma HLS protocol
Task-level Pipeline	pragma HLS dataflow pragma HLS stream
Pipeline	pragma HLS pipeline pragma HLS occurrence
Loop Unrolling	pragma HLS unroll pragma HLS dependence
Loop Optimization	pragma HLS loop_flatten pragma HLS loop_merge pragma HLS loop_tripcount
Array Optimization	pragma HLS array_map pragma HLS array_partition pragma HLS array_reshape
Structure Packing	pragma HLS data_pack