RTL Kernel Wizard General Settings

Kernel Identification

  • Kernel name:The kernel name. This will be the name of the IP, top level module name, kernel, and C/C++ functional model. This identifier shall conform to C and Verilog identifier naming rules. It must also conform to Vivado® IP integrator naming rules, which prohibits underscores except when placed in between alphanumeric characters.

  • Kernel vendor: The name of the vendor. Used in the in the Vendow/Library/Name/Version (VLNV) format described in

    Vivado Design Suite User Guide: Designing with IP (UG896).

  • Kernel library: The name of the library. Used in the VLNV. Must conform to same identifier rules Kernel name.

Kernel Options

Kernel type - Supports RTL and Block Design kernel types. A RTL kernel type consists of a Verilog RTL top level module with a Verilog control register module and a Verilog kernel example inside the top.Block Design kernel type also delivers a Verilog RTL top level module, but instead it instantiates an IP integrator Block Diagram inside of a verilog RTL top level module. The block design consists of MicroBlaze™ subsystem that uses a BRAM exchange memory to emulate the control registers. Example MicroBlaze software is delivered with the project to demonstrate using the MicroBlaze to control the kernel.

Clocking Options

Number of clocks - Sets the number of clocks used by the kernel. Every kernel has a primary clock and reset called ap_clk and ap_rst. All AXI interfaces on the kernel will be driven with this clock and reset. When Number of clocks is set to 2, a secondary clock and related reset are provided to be used by the kernel internally. The secondary clock and reset are called ap_clk_2 and ap_rst_n_2, respectively. This secondary clock supports independent frequency scaling and is independent from the primary clock. The secondary clock is useful if the kernel clock needs to run at a faster/slower rate than the AXI4 interfaces, which must be clocked on the primary clock. When designing with multiple clocks, proper clock domain crossing techniques must be used to ensure data integrity across all clock frequency scenarios.