Interface Requirements for Integration Into the Platform

The RTL kernel must adhere to the C function interface shown in the previous section. The RTL kernel must also integrate into a platform, which has its own requirements. The RTL kernel integrates into a platform using a slave AXI4-Lite interface for control register access (to pass kernel arguments and to start/stop the kernel). The RTL kernel can also have AXI4 master interfaces to talk to memory.

The interface requirements are discussed below in detail. In summary they are as follows:

The following signals and interfaces are required on the top level of an RTL block.

• Primary clock input port named ap_clk.
  • There can be a secondary optional clock input named ap_clk_2.
• Primary active low reset input port named ap_rst_n.
  • This signal should be internally pipelined to improve timing.
  • This signal is driven by a synchronous reset in the ap_clk clock domain.

• There can be a secondary optional active low reset input ap_rst_n_2.

  • This signal should be internally pipelined to improve timing.
  • This signal is driven by a synchronous reset in the ap_clk_2 clock domain.

• One and only one AXI4-Lite slave control interface.

  • Offset 0 of the AXI4-Lite slave interface must have the following signals:
    • Bit 0: start signal - The kernel starts processing data when this bit is set.
    • Bit 1: done signal - The kernel asserts this signal when the processing is done. This bit is clear on read.
    • Bit 2: idle signal - The kernel asserts this signal when it is not processing any data. The transition from low to high should occur synchronously with assertion of done signal.
  • The host typically writes to 0x00000001 to the offset 0 control register which sets Bit 0, clears Bits 1 and 2, and polls on reading done signal until it is a "1".
• One or more AXI4 memory mapped (MM) master interfaces for global memory.
  • All AXI4 MM master interfaces must have 64-bit addresses.
  • The kernel developer is responsible for partitioning global memory spaces. Each partition in the global memory becomes a kernel argument. The memory offset for each partition must be set by a control register programmable via the AXI4-Lite Slave interface.
  • AXI4 masters must not use Wrap or Fixed burst types, and must not use narrow (sub-size) bursts meaning AxSIZE should match the width of the AXI data bus.

Any user logic or RTL code that does not conform to the requirements above, must be wrapped or bridged to satisfy these requirements.