Editor’s Note: This content is contributed by Snehal Ullagaddi, Software & AI Marketing at Xilinx

 

To capitalize on the benefits of system integration, design teams require state of the art hardware architectures, design flows, and a proven methodology that maximizes productivity from concept through implementation and debugging. The Vivado® Design Suite has offered a new approach for ultra-high productivity with next-generation C/C++ and IP based design. To maximize system performance and enable accelerated and predictable design cycles, Vivado Design Suite 2020.1 introduced many features. Let’s take a look at some of the major highlights in the 2020.1 release.

 

Installation and User Interface Improvements

Web Installer allows you to download only what you need! Use this option to select and install your desired edition of Vivado Design Suite.

Web Installer allows you to download full images containing all devices and tool options without running installation. Use this option to install a full image on your network drive or to allow different users maximum flexibility when installing. Use Web Installer to install Vivado HL WebPACK™ and cut your download time by up to 2/3 and the download size by up to 6GB!

<Web Installer>

 

IP Integrator Improvements

IP integrator has several enhancements in the 2020.1 release. For example, the latest address editor provides real-time error highlighting and cross probing. The new addressing view offers a simplified view for addressable content only, and a cleaner view of addressing connectivity. It helps users to develop and debug easier than before.

<New “Addressing View” emotional view>

 

Design Analysis and Timing Closure Improvements

While users want to implement perfect solutions, it is always good to confirm that the design can perform at the highest level. Report QoR suggestions predict up to three custom strategies for better performance. The design analysis predicts and provides better results than Default and Performance_Explore, saves compile time and minimizes the effort to sweep many strategies. It even runs report_qor_assessment (RQA) to check if the design is compatible with the strategy prediction.

<QoR Suggestions>

Dynamic Function eXchange (DFX) Improvements

Nested DFX allows users to place one ore more dynamic regions within a dynamic region to further extend the flexibility of DFX solutions. Nested DFX is available in UltraScale™ and UltraScale+™ devices. With Nested DFX, the verification process is simpler, granularity is improved, and the uptime of Alveo™ data center accelerator cards is faster. Keep in mind that all existing IP for partial reconfiguration have been superseded by equivalent IP with Dynamic Function eXchange terminology, therefore, IP is easily upgradable from partial reconfiguration to DFX.

<Dynamic Function eXchange>

 

Power Rail based Reporting Now Available

Yes, that’s right. Power rail-based reporting is now available in the Vivado 2020.1 release. Power rail definitions are included in the board files by default. Power reports in the Vivado Design Suite calculate total current vs. current budgets for both rails and supplies.

<Power Analysis>

 

In summary, the Vivado Design Suite 2020.1 release provides

• Ability to select full image or selected products as part of Web installer 
• Address map enhancements for real-time error highlighting and cross probing
• Report QoR suggestions that predict up to 3 custom strategies for improved performance 
• Nested DFX, which further extends flexibility of DFX solutions
• Power rail based reporting

 

Download Vivado 2020.1 with latest features and new functionalities for greater productivity than even before.

To learn more about What's New in the Vivado 2020.1, read the release notes.

Xilinx also offers many new and updated user guides to help designers to jump start their development. Check them out! Visit here.

 

Original Date: 07-09-2020