AR# 8455

描述

How does the Port Enable pin work?

解决方案

The XPLA3 JTAG pins can be used as dual-purpose I/O to increase the I/O count when needed. The Port Enable pin is unique to the CoolRunner XPLA3 family. 

This pin allows the easy re-establishment of the JTAG IS pins if these pins have been used as regular I/O after programming. You can use one of the following to utilize the JTAG pins for the XPLA3 family:

• Use JTAG dedicated 
• Use JTAG pins as regular I/O (JTAG disabled) 
• Use JTAG pins as both JTAG and I/O  

JTAG Dedicated

Software:

The JTAG pins are dedicated or reserved by default. To verify this, ensure that the "Reserve ISP pins" option is checked. To find this option in the ISE software, right-click Implement Design -> Process -> Properties -> Advanced tab ->"Reserve ISP pins."

If this tab is not available, turn on the Advanced Options by selecting Edit -> Preferences -> Processes Tab and selecting "Advanced."

Hardware:

Tie the Port Enable pin Low.

I/O Only (JTAG disabled)

Software:

Uncheck the "Reserve ISP Pins" option. To find this option in the ISE software, right-click Implement Design -> Process -> Properties -> Advanced tab ->"Reserve ISP pins."

If this tab is not available, turn on the Advanced Options by selecting Edit -> Preferences -> Processes Tab and selecting "Advanced." Pin-assign your signals to the JTAG pins as you would any other I/O pin.

Hardware:

Tie the Port Enable pin to ground.

JTAG Pins as Both JTAG and I/O

Software:

Uncheck the "Reserve ISP Pins" option. To find this option in the ISE design tools, right-click Implement Design -> Process -> Properties -> Advanced tab ->"Reserve ISP pins." 

If this tab is not available, turn on the Advanced Options. Do this by selecting Edit -> Preferences -> Processes Tab and selecting "Advanced." Pin-assign your signals to the JTAG pins as if they are any other I/O pin.

Hardware:

The Port Enable pin must be Low on power-up. If this is not the case, improper self-configuration can occur. 

When the Port Enable pin is Low, the JTAG pins function as regular I/O. 

When the Port Enable pin is High, the JTAG pins resume their JTAG function. You can determine the implementation.

For other common CPLD questions, see the Tech Tips FAQ for Xilinx CPLDs (Xilinx Answer 24167)