AR# 7648

描述

What are the characteristics of I/Os during power-up and power-down for Xilinx CPLDs?

解决方案

CoolRunner-II

All I/Os stay in a 3-state condition with a weak pull-up to VCCIO during power up and power down.

When the device is powering up, an internal voltage sense circuit monitors VCC. When it determines that the potential is sufficient to "run" the chip, it starts a configuration process that concludes with the release of the I/O to the mode defined by the design. This voltage level is approximately 1.3V (not guaranteed). If the weak pull-up is not desired, you may place a 4.7k Ohm pull-down resistor on each pin that you wish to hold Low throughout configuration.

During power down, when the VCC monitor senses that the voltage has dropped to approximately 1.2V (not guaranteed), the I/Os are placed back into 3-state before the integrity of the internal logic is lost.

XPLA1 and XPLA3

All I/Os stay in a 3-state condition with a weak pull-up to VCC during power up and power down.

When the device is powering up, an internal voltage sense circuit monitors VCC. When it determines that the potential is sufficient to "run" the chip, it starts a configuration process that concludes with the release of the I/O to the mode defined by the design. This voltage level is approximately 2.4V (not guaranteed). If the weak pull-up is not desired, you may place a 4.7k Ohm pull-down resistor on each pin that you wish to hold Low throughout configuration.

During power down, when the VCC monitor senses that the voltage has dropped to approximately 2.1V (not guaranteed), the I/Os are placed back into 3-state before the integrity of the internal logic is lost.

XC9500/XL/XV

This behavior is described in the family datasheet under the section labelled Power-Up Characteristics.

For other common CPLD questions, please see the CPLD FAQ: (Xilinx Answer 24167).