Version Found: Vivado 2020.3
Timing violations might be seen with PL-PCIe blocks for XCVC1902 and other devices in the Versal Prime and AI core series with -1LP speed grade in the Gen4x8 configuration.
Additional implementation strategies or floor planning might be required to meet timing with this speed grade for this configuration.
This article is part of the PCI Express Solution Centre
| (Xilinx Answer 34536) | Xilinx Solution Center for PCI Express |
Xilinx Forums:
Please seek technical support via the PCI Express Board. The Xilinx Forums are a great resource for technical support.
The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.
This is a known issue which is planned to be fixed in a future release.
For the current status on known issue fixes, see (Xilinx Answer 73083).
Revision History:
| AR# 76357 | |
|---|---|
| 日期 | 04/14/2021 |
| 状态 | Active |
| Type | 已知问题 |
| IP | |