The issue can occur for a Mutli-bank interface configuration if the Single Bank has both RX and TX where the serialization factors are different or if enable_all_ports is used on the Advanced Tab.
An updated deskew circuitry for the PLL will be provided in a future version of the Advanced IO Wizard to resolve the timing violations.
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
73634 | Versal Advanced IO Wizard - Known Issue List | N/A | N/A |
AR# 76343 | |
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日期 | 06/21/2021 |
状态 | Active |
Type | 已知问题 |
器件 | |
Tools |