Version Found: Vivado 2020.2
Version Resolved and other Known Issues (Xilinx Answer 57945)
When the "Auto RxEq" option is enabled, link issues can occur where a Gen3 design trains down to Gen1 rate.
This article is part of the PCI Express Solution Centre
| (Xilinx Answer 34536) | Xilinx Solution Center for PCI Express |
This issue is seen in Vivado 2020.1 and Vivado 2020.2. It will be fixed in a future Vivado release. For the latest status on known issue fixes, see (Xilinx Answer 57945).
A patch has been provided to fix the issue in Vivado 2020.1 and Vivado 2020.2. For instruction on installing the patch, please check the instructions in the 'patch_readme' directory in the attached patch file.
Revision History:
02/23/2021 - Initial Release
| 文件名 | 文件大小 | File Type |
|---|---|---|
| AR76024_Vivado_2020_1_preliminary_rev1.zip | 1001 KB | ZIP |
| AR76024_Vivado_2020_2_preliminary_rev1.zip | 1007 KB | ZIP |
| AR# 76024 | |
|---|---|
| 日期 | 02/23/2021 |
| 状态 | Active |
| Type | 已知问题 |
| IP | |