AR# 75826

描述

This is a known issues article for the UltraScale+ GTM IBERT.

Version Found: ​This issue appears in all Vivado versions since IBERT GTM became available up to 2020.2.

Version Resolved and other Known Issues: See (Xilinx Answer 72071)

The Vivado IBERT status window in the hardware manager shows the incorrect error counter value.

The IBERT error counter only reads the LSB of the GTM COE error counters. i.e. The total counter is 32-bits wide, but IBERT only reports the lower 16-bits.

This results in IBERT reporting an incorrect error counter value, and a wrong (optimistic) Pre-FEC BER value when using PRBS (raw) mode.

This issue does not affect FEC mode because it uses different status registers to read pre-FEC BER.

解决方案

This issue is resolved in the 2020.2 release.

For earlier Vivado versions affected by this issue, users can read the bit error counts from the COE_STATUS_CH[0/1]_RX_PRBSERR_LSB and COE_STATUS_CH[0/1]_RX_PRBSERR_MSB registers and manually calculate the BER.

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