In Vivado 2020.1, the error below might be issued in some Versal design cases:
ERROR: [Place 30-859] Some BRAM area constraints are over utilized.
2 or more BRAM failed to place. The unplaced BRAM are constrained as below: (listing maximum of 20 BRAMs per constraint)
Area constraint: ClockRegion
design_1_i/design_path/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_0
Tile rectangles examined:
Rect: ((511, 404), (555, 523))
Number of BRAM required by this constraint: 1
Number of BRAM available in this constraint region: 0
Area constraint: Tool:Combined
design_1_i/design_path/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_0
Tile rectangles examined:
Rect: ((511, 404), (555, 523))
Rect: ((511, 284), (555, 403))
Number of BRAM required by this constraint: 1
Number of BRAM available in this constraint region: 0
A tactical patch has been created to fix the issue and is attached to this Answer Record.
It contains a "readme" file which includes installation instructions.
This patch is targeted for the 2020.1 release of Vivado.
(Xilinx Answer 66722) contains information on how to apply the patch using the XILINX_PATH environmental variable.
| 文件名 | 文件大小 | File Type |
|---|---|---|
| AR75389_vivado_2020_1_preliminary_rev1.zip | 76 MB | ZIP |
| AR# 75389 | |
|---|---|
| 日期 | 08/12/2020 |
| 状态 | Active |
| Type | 综合文章 |
| 器件 | |