General Description: FPGA Express removes the BSCAN_VIRTEX from the design before optimization. (This can occur in both VHDL and Verilog designs.)
解决方案
1
VHDL:
If this occurs in a VHDL design, place a dont_touch attribute on the instantiation in the HDL code to prevent it from being removed. This must be done within the code (as opposed to with the FPGA Express Constraints Editor), as the component is removed before the attribute can be applied within the editor. ... component BSCAN_VIRTEX port (TDO1, TDO2 : in STD_LOGIC; RESET, UPDATE, SHIFT, DRCK1, DRCK2, SEL1, SEL2, TDI : out STD_LOGIC ); end component;
attribute fpga_dont_touch : string; attribute fpga_dont_touch of U1 : label is "true";
If this occurs in a Verilog design, create an empty module declaration for the component that is being removed. This will define the port directions and allow FPGA Express to insert the component correctly. ... BSCAN_VIRTEX U1 (.TDO1(TDO1), .TDO2(TDO2), .RESET(RESET), .SHIFT(SHIFT), .UPDATE(UPDATE), .DRCK1(CLK1), .DRCK2(CLK2), .SEL1(SEL1), .SEL2(SEL2), .TDI(TDI)); ... endmodule