2. 技术支持
  3. AR# 7203:
  4. AR# 72034: DMA / Bridge Subsystem for PCI Express and UltraScale+ PCI Express Integrated Block (Vivado 2018.3) - Endpoint Generation fails with xqzu5ev-ffrb900-1M-m device for Gen2 (5.0 GT/s) and 125MHz AXI Clock Frequency

AR# 72034

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DMA / Bridge Subsystem for PCI Express and UltraScale+ PCI Express Integrated Block (Vivado 2018.3) - Endpoint Generation fails with xqzu5ev-ffrb900-1M-m device for Gen2 (5.0 GT/s) and 125MHz AXI Clock Frequency

描述

Version Found:

  • DMA / Bridge Subsystem for PCI Express v4.1 (Rev. 2) - (Vivado 2018.3)
  • UltraScale+ PCI Express Integrated Block v1.3 (Rev. 4) - (Vivado 2018.3)

Version Resolved and other Known Issues: 

DMA Subsystem for PCI Express (Xilinx Answer 65443) / UltraScale+ PCI Express Integrated Block (Xilinx Answer 65751)

The tactical patch provided with this Answer Record provides the following fix:

  • Bug Fix: Allow Gen2 (5.0 GT/s) and 125 MHz AXI Clock Frequency with the xqzu5ev-ffrb900-1M-m device

解决方案

The issues listed in this answer record will be fixed in a future release of the core.

For instructions on installing the patch, please check the instructions in the 'patch_readme' directory in the attached patch file.

Note: The "Version Found" lists the version where the problem was first discovered.

The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:

02/15/2019 - Initial Release

附件

文件名 文件大小 File Type
AR72034_Vivado_2018_3_preliminary_rev1.zip 9 MB ZIP

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
65443 DMA Subsystem for PCI Express - Release Notes and Known Issues for Vivado 2015.3 and newer tool versions N/A N/A
65751 UltraScale+ PCI Express Integrated Block - Release Notes and Known Issue N/A N/A
AR# 72034
日期 02/22/2019
状态 Active
Type 已知问题
器件
Tools
IP
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