Version Found: v4.0(Rev1) / v4.1
Version Resolved and other Known Issues: (Xilinx Answer 65443)
In Vivado 2017.4 and Vivado 2018.1, the DMA Subsystem for PCI Express IP does not allow the user to set the "PCIe to DMA Bypass Interface" BAR size setting to 32GB if 64 bit is enabled.
It is limited to a 2GB size.
This issue was not present with this IP in Vivado 2017.3 or earlier versions.
It is observed only when targeting the IP to non UltraScale+ devices.
This article is part of the PCI Express Solution Centre
(Xilinx Answer 34536) | Xilinx Solution Center for PCI Express |
This is a known issue to be fixed in a future release of the core.
To fix the issue in Vivado 2017.4 and 2018.1, please install the respective patches provided in this answer record.
For instruction on installing the patch, please check the instructions in the 'patch_readme' directory in the attached patch file.
Revision History:
04/30/2018 - Initial Release
文件名 | 文件大小 | File Type |
---|---|---|
AR71012_Vivado_2018_1_preliminary_rev1.zip | 4 MB | ZIP |
AR71012_Vivado_2017_4_preliminary_rev1.zip | 4 MB | ZIP |
AR# 71012 | |
---|---|
日期 | 04/30/2018 |
状态 | Active |
Type | 已知问题 |
IP |