AR# 70012

描述

Version Found:

• DMA / Bridge Subsystem for PCI Express v4.0 - (Vivado 2017.3)
• UltraScale+ PCI Express Integrated Block v1.3 - (Vivado 2017.3)

Version Resolved and other Known Issues: DMA Subsystem for PCI Express (Xilinx Answer 65443) / UltraScale+ PCI Express Integrated Block (Xilinx Answer 65751)

The issues listed in the patch might have existed in previous versions of the core.

The tactical patch provided with this Answer Record provides the following fixes and enhancements:

DMA / Bridge Subsystem for PCI Express v4.0 - (Vivado 2017.3)

All of the issues listed are for both DMA Mode and Bridge Mode

• Bug Fix: Corrected MSI-X Table Size to 'h1F (32 vectors).
• Bug Fix: Corrected CC to TX conversion which was causing register read failures when there is high C2H traffic. (affects 7 Series and Zynq-7000 devices only)
• Bug Fix: Fixed the receive data for PCIe Hard Block when 64-bit addressing is enabled. (affects 7 Series and Zynq-7000 devices only)
• Bug Fix: Corrected ext_sys_clk_bufg option. (affects UltraScale+ devices only)
• Bug Fix: Corrected sys_clk BUFG path in ip_pcie4_uscale_late.xdc file when ext_sys_clk_bufg option is set to TRUE. (affects UltraScale+ devices only)
  

All of the issues listed are for Bridge Mode only

• Bug Fix: Allow MSI-X Table and PBA registers to be programmed while MSI-X Enable bit in MSIX Control register is 0.

UltraScale+ PCI Express Integrated Block v1.3 - (Vivado 2017.3)

• Bug Fix: Corrected sys_clk BUFG path in ip_pcie4_uscale_late.xdc file when ext_sys_clk_bufg option is set to TRUE
• Bug Fix: Corrected multicycle path constraints for design with 512-bit AXI Stream interfaces.
  

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express

解决方案

This issue will be fixed in the next release of the core. Please install the patch in Vivado 2017.3 as described below:

METHOD 1:

1. Navigate to the $XILINX_VIVADO/patches directory (create this directory if it does not exist)
2. Extract the contents of the ".zip" archive to a directory starting with the name AR70012
   Note: most extraction tools will allow you to automatically create a directory with the same name as the zip file
3. Run Vivado software tools from the original install location.
   

METHOD 2:

1. Create a separate directory for the patched files
2. Extract the contents of the ".zip" archive to the desired patch directory location
3. Set the MYVIVADO environment variable to point to the Vivado directory under this patch directory
   For example:
   set MYVIVADO=C:\MYVIVADO\vivado-patch-AR70012vivado\
4. Run Vivado software tools from the original install location.

Instantiate BUFG_GT / BUFG_GT_SYNC external to the IP and IP Properties:

This fixes an issue where sharing sys_clk from the PCI Express IBUFDS_GTE4 between two or more components causes design not to route.

This must be done prior to "Open Example Design". With this patch, after "Open Example Design" Step 3 and 4 will be executed automatically.

1. In the DMA Subsystem for PCI Express or PCI Express Integrated Block, set the following property in the Vivado Tcl console:
   

• For non-IP Integrator (non-Block Design) flow:

set_property CONFIG.ext_sys_clk_bufg true [get_ips <ip_name>]

• For IP Integrator (Block Design) flow:

set_property CONFIG.ext_sys_clk_bufg true [get_bd_cells <ip_name>]

2. Reset Output Products on the IP or your Block Design and Regenerate Output Products again to have the new settings applied to the design.
   
3. Instantiate BUFG_GT and BUFG_GT_SYNC in your design as follows:

wire sys_clk_bufg;
wire sys_clk_ce_out;
wire sync_sc_ce;
wire sync_sc_clr.

BUFG_GT bufg_gt_sysclk (.CE (sync_sc_ce), .CEMASK (1'd0), .CLR (sync_sc_clr), .CLRMASK (1'd0), .DIV (3'd0), .I (sys_clk), .O (sys_clk_bufg));
BUFG_GT_SYNC sys_sys_clk (.CESYNC(sync_sc_ce), .CLRSYNC (sync_sc_clr), .CE(sys_clk_ce_out), .CLK(sys_clk), .CLR (1'b0));

4. Add/Replace the following ports in your DMA Subsystem for PCI Express or PCI Express Integrated Block IP instantiation:

.sys_clk ( sys_clk_bufg ),
.sys_clk_ce_out (sys_clk_ce_out)

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