I am attempting to exercise the interfaces on the Virtex UltraScale+ VCU118 Evaluation Kit.
What tests can be run to ensure that the interfaces are working correctly?
Virtex UltraScale+ FPGA VCU118 Evaluation Kit Documentation and Example Designs referenced below can be found on the VCU118 Support page.
| Feature | Test Design | Notes |
|---|---|---|
| -- Configuration Interfaces -- | ||
| Configuration Mode Switches | VCU118 User Guide (UG1224) | Table has the valid settings. Assuming configuration source is correctly programmed, this can test the mode pins. |
| Configuration USB JTAG port | VCU118 Board Interface Test (XTP439) | |
| Configuration BPI Flash | VCU118 Board Interface Test (XTP439) | |
| -- Board Feature Interfaces -- | ||
| Board DDR4 DIMM | VCU118 Board Interface Test (XTP439) | Also tested with the VCU118 MIG Example Design (XTP442) |
| Board PCIe Edge Connector | VCU118 PCIe Example Design (XTP444) | |
| Board SFP Connector | VCU118 GT IBERT Example Design (XTP440) | Requires additional hardware (see XTP449) |
| Board Oscillator ( MHz, Differential) | VCU118 Board Interface Test (XTP439) | The default BIT examples use the socket clock |
| Boards RJxx - Ethernet | VCU118 Board Interface Test (XTP439) | |
| Board USB Serial UART | VCU118 Board Interface Test (XTP439) | |
| Board I2C Interface | VCU118 Board Interface Test (XTP439) | |
| Board FMC-HPC Connector | XM105 User Guide (UG537) | Page 29. This is the User Guide for the XM105 Mezzanine Debug Card. This card has DS5, DS6, and DS7, which indicate good power to the board. Debug strategies will vary depending on the specific mezzanine card being used. |
| -- Transceiver Interfaces -- | ||
| Transceiver RefCLK (differential) | VCU118 GT IBERT Example Design (XTP440) | This is the IBERT Example Design and could be modified to use SMA RefCLK |
| Transceiver SMA Connectors (Differential) | VCU118 GT IBERT Example Design (XTP440) | |
| -- User Specified Interfaces -- | ||
| User SMA CLK Connectors (Differential) | none available | These are completely user-driven I/O. A good test would be loop back or monitoring differential I/O on a scope |
| User LEDs | VCU118 Board Interface Test (XTP439) | |
| User DIP Switches | VCU118 Board Interface Test (XTP439) | |
| User Pushbuttons | VCU118 Board Interface Test (XTP439) | |
| User LCD Display | VCU118 Board Interface Test (XTP439) |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 69737 | Virtex UltraScale+ FPGA VCU118 Evaluation Kit - Board Debug Checklist | N/A | N/A |
| 43748 | Xilinx Boards and Kits - Debug Assistant | N/A | N/A |
| AR# 69835 | |
|---|---|
| 日期 | 10/02/2017 |
| 状态 | Active |
| Type | 综合文章 |
| Boards & Kits | |