This answer record lists the known issues for simulation in the Vivado 2017.x releases.
Each known issue includes a link to another answer record that contains additional information on the issue.
Outstanding Issues in Vivado 2017.2
| (Xilinx Answer 69251) | 2017.1/2 Vivado Simulator - ERROR: [XSIM 43-3316] Signal SIGSEGV received |
| (Xilinx Answer 69252) | 2017.1/2 - compile_simlib passes incorrect switch to SecureIP compilation targeting Active HDL |
Outstanding Issues in Vivado 2017.1
| (Xilinx Answer 67272) | Vivado Simulator 2016.1 - ERROR: [XSIM 43-3238] Failed to link the design |
| (Xilinx Answer 67890) | 2016.3 - Vivado Simulator - Scope for pre-compiled IP instance is missing in Scope Window |
Issue resolved in Vivado 2017.1
| (Xilinx Answer 67870) | 2016.3 - Compile Simlib - Error in XPM library compilation when -ise_install_path option is used |
| (Xilinx Answer 68778) | Vivado Simulator - No ports or signals are dumped to SAIF file when the entity is instantiated inside generate block |
| AR# 69048 | |
|---|---|
| 日期 | 10/02/2017 |
| 状态 | Active |
| Type | 已知问题 |
| Tools | |