2. 技术支持
  3. AR# 6839:
  4. AR# 68398: Zynq UltraScale+ MPSoC: 2016.4 FreeRTOS_SetupTickInterrupt does not disable timer IRQ before it initializes the GIC.

AR# 68398

|

Zynq UltraScale+ MPSoC: 2016.4 FreeRTOS_SetupTickInterrupt does not disable timer IRQ before it initializes the GIC.

描述

In OpenAMP, when RPU is running I stop it and then start it again.

The RPU hangs at 0x18 (the IRQ exception entry), after it registers the timer IRQ in the FreeRTOS_SetupTickInterrupt() of portZynqUltrascale.c.

解决方案

Apply the attached patches to resolve this issue.

  • R5 processor interrupts needs to be enabled after initialization of TTC time in the FreeRTOS_SetupTickInterrupt function with the patch 0002-ThirdParty-bsp-R5-Updated-FreeRTOS_SetupTickInterrup.patch
  • Mapping of CPU with SPI interrupts needs to be removed by the OpenAMP firmware application, on shutdown request from Linux.
    0001-scugic-Added-API-XScuGic_RemoveInterruptMappingToCpu.patch provides the API "XScuGic_RemoveInterruptMappingToCpu" to remove mapping of current CPU with SPI interrupts.
    It needs to be invoked from the shutdown flow of the OpenAMP firmware application, as is done in the attached patch 0003-sw_apps-openamp_echo_test-Remove-CPU-mapping-to-SPI-.patch

附件

文件名 文件大小 File Type
0001-scugic-Added-API-XScuGic_RemoveInterruptMappingToCpu.patch 2 KB PATCH
0002-ThirdParty-bsp-R5-Updated-FreeRTOS_SetupTickInterrup.patch 1 KB PATCH
0003-sw_apps-openamp_echo_test-Remove-CPU-mapping-to-SPI-.patch 1 KB PATCH
AR# 68398
日期 12/21/2016
状态 Active
Type 综合文章
器件
Tools More Less
Boards & Kits
People Also Viewed