2. 技术支持
  3. AR# 6696: LogiCORE PCI - During simulation, pull-ups must be placed on all signals designated s/t/s in the specification
  4. AR# 66969: MIG 7 Series - Cannot select 72-bit data width in the MIG wizard GUI when the part is XC7Z035FFG676-2

AR# 66969

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MIG 7 Series - Cannot select 72-bit data width in the MIG wizard GUI when the part is XC7Z035FFG676-2

描述

Version Found: v2.4 Rev1

Version Resolved: See (Xilinx Answer 54025)

I cannot select 72 bit data width in the MIG wizard when the part is XC7Z035FFG676-2, and there is a warning as shown in the following screen capture:





However, for the pin compatible parts 7Z030FFG676-2 and 7Z045FFG676-2, I can select 72 bit data width. Is this a limitation with the IP for 72 bit data width?





  

解决方案

This is a MIG wizard GUI issue.

To work around this issue please follow the steps below:

  1. Use an XC7Z030-2FFG676C or XC7Z045-2FFG676 Fixed Pinout to generate the MIG project, selecting pin compatible FPGAs XC7Z035-2FFG676C in the wizard GUI. .prj and .xdc files for the IP will be generated.
  2. Create a new project for an XC7Z035-2FFG676C, and use the generated IP files in the first step (.prj and .xdc) with the "Verify pin changes and update design" flow to generate the IP for the XC7Z035.

 

Revision History

12/06/2016 - Initial release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 66969
日期 09/14/2016
状态 Active
Type 已知问题
器件
Tools
IP
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