AR# 66114

描述

I have a Block Design (BD) which has a Video processing subsystem and interconnect.

When I validate my Block Design in Vivado 2015.3 or 2015.4 I get the following error.

ERROR: [BD 41-237] Bus Interface property DATA_WIDTH does not match between /axi_mem_intercon/m01_couplers/auto_pc/S_AXI(32) and /axi_mem_intercon/m01_couplers/auto_cc/M_AXI(512)
validate_bd_design: Time (s): cpu = 00:00:43 ; elapsed = 00:01:18 . Memory (MB): peak = 7196.344 ; gain = 0.000 ; free physical = 6140 ; free virtual = 33871
ERROR: [Common 17-39] 'validate_bd_design' failed due to earlier errors.

解决方案

Parameter propagation is not being correctly run for designs which have a Video processing subsystem and interconnect.

When Vivado queries IP Integrator for parameter conflicts, no DATA_WIDTH conflict is reported during the conflict resolution stage:

Because no DATA_WIDTH mismatch is reported, interconnect does not insert any width conversion.

To work around the issue, do the following:

1. Insert an AXI Protocol Converter module between the Interconnect and Video Processing Subsystem
2. Configure M_AXI output of the AXI Protocol Converter to AXI4_LITE

This issue is fixed in Vivado 2016.1.