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  3. AR# 6606: 4.1i FPGA Editor - Resizing the "Array", "Edit Block" or "World" window does not update the size of the FPGA image on HPUX.
  4. AR# 66062: Vivado Simulator 2015.4 - FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover

AR# 66062

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Vivado Simulator 2015.4 - FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover

描述

My design works correctly in Vivado 2015.3 but fails simulation with a fatal error in Vivado 2015.4.

FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover. 
Process will terminate. For technical support on this issue, please open a WebCase with this project attached at
Time: 0 ps Iteration: 0 Process: /tb_bug/test_p
File: /home/viv2015_4_bug/viv2015_4_bug/viv2015_4_bug.srcs/sources_1/new/tb_bug.vhd

HDL Line: /home/viv2015_4_bug/viv2015_4_bug/viv2015_4_bug.srcs/sources_1/new/tb_bug.vhd:51

The error points to a line where a function is called. Inside the function, a parameterized 2-D array is declared:

  type std_logic_2d is array(integer range <>, integer range <>) of std_logic;

  function bin_decode_chu (a  : std_logic_vector;
                           en : std_logic) return std_logic_vector is
    constant STAGE_C : natural := a'length;
    variable p       : std_logic_2d(STAGE_C downto 0, 2**STAGE_C-1 downto 0);

解决方案

The issue is due to incorrect optimization for 2-D arrays in VHDL.

A work-around is to do value propagation at the RTL stage.

For Example, change the line from:

variable p : std_logic_2d(STAGE_C downto 0, 2**STAGE_C-1 downto 0);

Change the line to:

variable p : std_logic_2d(5 downto 0, 2**5-1 downto 0);

This issue is fixed in Vivado 2016.1.

AR# 66062
日期 04/21/2016
状态 Active
Type 已知问题
器件
Tools
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