AR# 65606

描述

In V2.4 of MIG 7 series QDRII+, RLDRAM2 or RLDRAM3 interfaces, the GUI will report a false rule violation.

When a user chooses to either set fixed pinout, or to import XDC or UCF files into MIG, and if a port is targeted to the Vref pin, then the below error message will appear.

MIG should allow assigning of ports to a Vref pin location when a bank is write only, or to input when the internal Vref option is chosen.

Error Message:

The port <Portname> is allocated in the bank <bankno> where the input ports are allocated. Enable the Internal Vref to use the Vref as GPIO

Applicable memory type: QDRII Plus, RLDRAM2, RLDRAM3

Applicable MIG version: MIG 7 series v2.4

解决方案

The solution is to downgrade the corresponding error to a warning. 

To downgrade the message, a change is required to mig_verify.xml which controls the MIG GUI rule checking. The attached patch will demote the error message to a warning and the MIG IP can be generated as expected.

To install the patch, extract the contents of "AR65606_vivado_2015_3_preliminary_rev1" to the 2015.3 install directory (for example, C:\Xilinx\Vivado\2015.3\), then open Vivado 2015.3 and use MIG. 

附件