AR# 65414

描述

This Design Advisory is being released as a notification of calibration updates provided with MIG 7 Series v2.4, available with Vivado 2015.3, which provide additional margin for QDRII+, RLDRAM3, and RLDRAM2 IP.

The updates are included in MIG 7 Series v2.4 QDRII+, RLDRAM3, and RLDRAM2 designs.

This answer record includes information regarding the updates and whether the updates are recommended within new and existing systems.

解决方案

Updates included in MIG 7 Series v2.4 are as follows:

• Write Calibration Updates: RLDRAM2 and QDRII+ SRAM interfaces that operate at 400MHz and above
• Read Calibration Updates: RLDRAM2, RLDRAM3, and QDRII+ complex read calibration that operate at 400MHz and above
• Additional Updates: 36-bit QDRII+ controller interfacing to two 18bit components for all frequency

Details of Write Calibration changes:

Write K centering within the write D eye has previously consisted of finding window edges through adjustment of Phaser_OUT taps.
This algorithm has been seen across process variation to place the write strobe Phaser_OUT taps in a non-ideal (non-center) location, causing the Write clock to be shifted either left or right of the true center.

The new algorithm uses a MMCM to perform precise phase adjustments to determine the window and place the write strobe in the true center of the write data eye.
No additional MMCM is added. Instead, the MMCM already included in MIG generated designs to create the fabric clock "PHY_Clk" is also used to perform this write side calibration.

However, a new MMCM output is added to perform the phase adjustments which requires an additional BUFG.

These updates to the write calibration logic increase the time for calibration to complete in hardware.
Calibration times are faster at higher frequencies because the required number of reads and writes to perform the phase adjustment can complete faster then at a lower frequency.
Calibration time in simulation when using the FAST mode is minimally affected.

Details on Read Calibration changes:

A revised pattern is used in complex read calibration that yields more precise window detection, for more read margin.

Details on QDRII+ controller interfacing to two 18bit components:

It is required to use v2.4 when interfacing with two 18-bit components to construct a 36-bit wide interface.
Prior to this version, write calibration can only calibrate the first component which is likely to cause calibration or data error.

Recommendations for updating MIG Versions:

For new designs and those not yet in production, please update to MIG 7 Series v2.4 to achieve maximum margin.
Updates are only applicable for RLDRAM2, RLDRAM3 and QDRII+ designs operating at and above 400MHz, or 36bit QDRII+ design using two 18bit components.

For systems already in production that have completed and passed system testing with no write margin failures, updating is recommended but not required.
Should a bitfile update in the production cycle be available, inclusion of MIG 7 Series 2.4 is recommended.

Please open a service request if it is difficult to make a decision on whether to update the design.