AR# 64421

描述

Version Found: MIG 7 Series v2.3

Version Resolved: See (Xilinx Answer 54025)

MIG 7 series AXI enabled DDR3 designs with ECC (72 bits) can fail in hardware.

解决方案

There is an RTL syntax issue in the Verilog file mig_7series_v2_3_ecc_gen.v

 for (index=0; index<ECC_WIDTH; index=index+1)
        begin
          // The "== 1'bx" is so this will converge at time zero.
          // XST assumes false, which should be OK.
          if ((&i == 1'bx) || trig1) next_combo[index] = i[index];
          else begin
            next_combo[index] = 1'b0;
            ones = ones + i[index];
            if (i[index] && seen0) begin
              trig1 = 1'b1;
              for (dump_index=index-1; dump_index>=0;dump_index=dump_index-1)
                if (dump_index>=index-ones) next_combo[dump_index] = 1'b1; 
            end              
            seen0 = ~i[index];
          end // else: !if(trig1)
        end        

The condition &i == 1'bx is expected to evaluate to false as per the comment. But this is not behaving as expected and an ECC error is reported.

As a work-around, update the RTL so that check for == 1'bx is removed.

Original:

if ((&i == 1'bx) || trig1) next_combo[index] = i[index];

New:

if (trig1) next_combo[index] = i[index];

This behavior is seen only on Hardware and not in simulation.

Please see (Xilinx Answer 57546) for details on how to edit IP RTL files.

Note: The "Version Found" column lists the version where the problem was first discovered. The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History

12/11/2015 - Initial Release

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