AR# 63988

At the post-synthesis simulation stage, although it is not typical, you can perform timing simulation with estimated timing numbers.
 

At the post-implementation simulation stage, timing simulation is the closest emulation to actually downloading a design to a device.

It allows you to ensure that the implemented design meets functional and timing requirements and has the expected behavior in the device.
 

NOTE: Post-Synthesis and Post-Implementation timing simulations are supported for Verilog only.
 
There is no support for VHDL timing simulation.

This article describes the two ways to run timing simulation using Vivado Simulator: from the Vivado IDE and from the command line.

1. In the Vivado project, run Synthesis or Implementation.
   
2. Specify Vivado Simulator Simulation Settings if necessary.
3. From the Flow Navigator, select
   Run Simulation > Run Post-Synthesis Timing Simulation
   or
   Run Simulation > Run Post-Implementation Timing Simulation.
   The option becomes available only when synthesis or implementation is run successfully.
    

1. Generate a Verilog timing simulation netlist for the design.
    
   

Example:
 

   2. Generate an SDF delay file with all the timing delays annotated.
 

Example:
 

   3. Parse the individual files or a project file, elaborate and generate a snapshot by appropriately annotating the SDF file, and then simulate.

      The Vivado simulator models use interconnect delays.

      As a result, additional switches are required for proper timing simulation, as follows:
 

Example:
 

For more information on using Vivado Simulator and the command line options, please refer to (UG900) Vivado Design Suite User Guide: Logic Simulation.