Background:
High read/write sample counts used in the 2014.2 to 2014.4 releases of MIG cause the increase in calibration time.
Examples of calibration times across releases are shown below.
To reduce the calibration time, Xilinx has performed hardware validation with reduced sample counts.
The reduced sample counts will be included in the Vivado 2015.1 release of MIG.
Until this version is available, a manual work-around is provided below.
Manual Changes to Reduce Calibration Time in MIG v2.3
1. Open the 'user_design/rtl/phy/mig_7series_v2_3_ddr_calib_top.v' module.
Reduce the OCAL sample counts as shown below.
localparam SAMPLES =
(SIM_CAL_OPTION=="NONE") ? 512 : 4; //original value of 2048
localparam
OCAL_SIMPLE_SCAN_SAMPS = (SIM_CAL_OPTION=="NONE") ? 512 : 1; //original value of 2048
2. Open the 'user_design/rtl/phy/mig_7series_v2_3_ddr_phy_prbs_rdlvl.v' module.
Reduce the loop count for complex read leveling as shown below.
localparam [11:0] NUM_SAMPLES_CNT = (SIM_CAL_OPTION == "NONE") ? 'd12 : 12'h001; //original value of 50
3. Manually synthesize the MIG IP.
Out of Context flow (OOC) cannot be used after modifying the IP rtl.
Note: Example files that include these changes are attached to this answer record.
Summary of Calibration Times
Release |
Cal time at 400 MHz (4:1) |
Cal time at 800 MHz (4:1) |
||
|
|
32-bit |
72-bit |
32-bit |
72-bit |
|
2014.1 |
less than 1 sec |
less than 1 sec |
less than 1 sec |
less than 1 sec |
|
2014.3 |
less than 1 sec |
~1 sec |
less than 1 sec |
little over 1 sec |
|
2014.4 |
less than 4 sec |
~7 sec |
less than 2 sec |
less than 4 sec |
|
Reduced samp count |
~1 sec |
~2 sec |
less than 1 sec |
~1 sec |
Note: The same number of reads and writes are performed for all MIG DDR3 configurations.
Therefore, as the interface width widens and/or the datarate decreases, the time to complete these reads/writes increases causing longer calibration times.
Related Answer Records:
(Xilinx Answer 62368)
Design Advisory for MIG 7 Series DDR3 - Calibration updates in MIG 7
Series v2.3 available with Vivado 2014.4 provide additional write margin
(Xilinx Answer 60687) MIG 7 Series DDR3 - Calibration updates available in MIG 7 Series v2.1
released with Vivado 2014.2 that provide additional read margin for data
rates above 1333Mbps
| 文件名 | 文件大小 | File Type |
|---|---|---|
| mig_7series_v2_3_ddr_phy_prbs_rdlvl.v | 238 KB | V |
| mig_7series_v2_3_ddr_calib_top.v | 88 KB | V |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 62368 | 面向 MIG 7 系列 DDR3 的设计咨询——Vivado 2014.4 版配套提供的 MIG 7 系列 v2.3 版校准更新提供了更多的写入裕度。 | N/A | N/A |
| 60687 | MIG 7 Series DDR3 - Calibration updates available in MIG 7 Series v2.1 released with Vivado 2014.2 that provide additional read margin for data rates above 1333Mbps | N/A | N/A |
| AR# 63463 | |
|---|---|
| 日期 | 02/13/2015 |
| 状态 | Active |
| Type | 综合文章 |
| 器件 | |
| IP | |