AR# 63260: LogiCORE IP SMPTE2022-5/6 Video Over IP Transmitter v4.0 (Rev. 2) - Why does the SMPTE2022-5/6 Tx sometimes ignore the non-block aligned configuration register?
AR# 63260
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LogiCORE IP SMPTE2022-5/6 Video Over IP Transmitter v4.0 (Rev. 2) - Why does the SMPTE2022-5/6 Tx sometimes ignore the non-block aligned configuration register?
描述
Why does the SMPTE2022-5/6 Tx sometimes ignore the non-block aligned configuration register?
解决方案
This is a known issue in the LogiCORE IP SMPTE2022-5/6 Video Over IP Receiver v4.0 (Rev. 1).
This is due to an issue in the core where sometimes it ignores the non-block alignedconfiguration register and produces block aligned outputs.
This issue has been resolved in the LogiCORE IP SMPTE2022-5/6 Video Over IP Receiver v4.0 (Rev. 2) core and later.
Vivado 2014.3 and Vivado 2014.4 users can obtain the latest patch from (Xilinx Answer 62827)