AR# 63149

描述

On initial device power up, when the PS PS_POR_B de-asserts within a certain timing window in relationship to power up of  the last PL power supply (VCCINT, VCCBRAM, VCCAUX or VCCO_0), the device can enter Secure Lockdown state and will prevent boot from completing per the lockdown specification.

This window is defined as a minimum and maximum time relative to the last PL power supply ramp:

Tslw (min) = Time from last PL power supply reaching 250mv  to start of Secure Lockdown Window

Tslw (max) = Time from last PL power supply reaching 250mv  to end of Secure Lockdown Window

解决方案

• Identify probe points for PS_POR_B, VCCINT (PL), VCCAUX (PL), VCCBRAM, VCCO_0 (PL).
• For PL supply, identify the probe points near to the die, typically on the supply bypass capacitor.
• Use an oscilloscope to measure the relative time between the signals for Test 1 and Test 2.

In the "Possible Risk" scenario, the power up sequence and de-assertion timing of PS_POR_B must be analyzed to determine if it falls within the Secure Lockdown timing window (Tslw).  

1. If you do an initial power-up AND
2. If you see a hang during boot AND
3. If you do not see an access to your boot device AND
4. If you see the PL JTAG TAP in the JTAG chain AND
5. If you do not see the PS JTAG TAP in the JTAG chain AND
6. INIT_B goes HIGH and stays HIGH after secure lockdown AND7.       If PS_POR_B de-assertion falls inside the Secure Lockdown window

• Change timing relationship between last PL power ramp and PS_POR_B using PCB level circuits (Preferred Solution)


• Change PS BootROM code execution time (*) to shift the window by
   
  
  • enabling 128K CRC check by burning a PS eFuse bit
  or
  • enabling PLL Bypass (**)

•  Results of the attached spreadsheet analysis (a snapshot of the timing in the spreadsheet)
•  Scope-shots of PS_POR_B, VCCINT (PL), VCCAUX (PL), VCCBRAM, VCCO_0 (PL) and INIT_B (the time relationship between the signals is required)

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