In Vivado 2014.3 and later releases, BRAM and FIFO models are not included in the UNIFAST simulation library:
<Vivado_Install_Dir>/data/vhdl(verilog)/src/unifast.
A number of issues have been reported with UNIFAST BRAM and FIFO models when they are involved in GT based design.
The limitation of features supported in fast BRAM/FIFO models versus the full models can make it difficult to take advantage of the simulation run time speed-up for GT.
One example is where the PCIe IP Example Design is using RAMB36E1 in a mode that is not supported by the fast model.
CLKARDCLK and CLKBWRCLK of RAMB36E1 are driven by a synchronous clock.
There is no sync clocks/collision support in the UNIFAST library for RAMB36E1.
Therefore if "-L unifast" is enabled, simulation fails with a time out error.
Because BRAM and FIFO UNIFAST models are rarely used and the runtime gain is less than 50% on these models, they have been removed from the list of UNIFAST models.
Please refer to each release of (UG900) Vivado Design Suite User Guide: Logic Simulation for a list of UNIFAST library models and their feature differences from the full models.
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 64053 | Xilinx Simulation Solution Center - Design Assistant - Simulation Libraries - UNIFAST | N/A | N/A |