受影响的器件如下:
//---------- Generate DCLK Buffer ----------------------------------------------
generate if (PCIE_USERCLK2_FREQ <= 3)
//---------- Disable DCLK Buffer -----------------------
begin : dclk_i
assign CLK_DCLK = userclk2_1; // always less than 125Mhz
end
else
begin : dclk_i_bufg
//---------- DCLK Buffer -------------------------------
BUFG dclk_i
(
//---------- Input ---------------------------------
.I (clk_125mhz),
//---------- Output --------------------------------
.O (CLK_DCLK)
);
end
endgenerate
//---------- Generate DCLK Buffer ----------------------------------------------
generate if (PCIE_LINK_SPEED != 1)
begin : dclk_i_bufg
//---------- DCLK Buffer -------------------------------
BUFG dclk_i
(
//---------- Input ---------------------------------
.I (clk_125mhz),
//---------- Output --------------------------------
.O (CLK_DCLK)
);
end
else
//---------- Disable DCLK Buffer -----------------------
begin : dclk_i
assign CLK_DCLK = clk_125mhz_buf;
end
endgenerate
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
53561 | 有关 Artix-7 FPGA GTP 收发器的设计咨询:量产芯片 RX 复位顺序要求 | N/A | N/A |
AR# 62770 | |
---|---|
日期 | 11/20/2014 |
状态 | Active |
Type | 设计咨询 |
IP |