Version Found: MIG 7 Series v2.3
A warning message similar to the following can be generated when upgrading a MIG 7 Series IP within a Vivado 2014.4 IPI block design that includes the usage of the additional MMCM output clocks:
[xilinx.com:ip:mig_7series:2.3 0] design_1_mig_7series_0_0: Clocking structure for MIG has been updated.
Additional Clkout0 value 100.000 MHz cannot be generated using the new specification.
Updated IP will use the nearest possible value of 99.279 MHz. Refer to AR62615 for more details.
This warning message is generated due to MMCM VCO frequency changes that were made along with the write calibration updates in MIG 7 Series v2.3.
A part of the write calibration changes is to include MMCM precise fine phase adjustments.
This requires M and D integer divide values.
Therefore, the VCO frequency change and affected available MMCM parameters can affect the available MMCM output frequencies.
Please see (Xilinx Answer 62368) for full details on the write calibration changes.
To work around this, select the closest clock frequency available in the MIG 7 Series GUI.
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 58435 | MIG UltraScale - IP Release Notes and Known Issues for Vivado 2014.1 and newer tool versions | N/A | N/A |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 62368 | 面向 MIG 7 系列 DDR3 的设计咨询——Vivado 2014.4 版配套提供的 MIG 7 系列 v2.3 版校准更新提供了更多的写入裕度。 | N/A | N/A |
| AR# 62615 | |
|---|---|
| 日期 | 11/24/2014 |
| 状态 | Active |
| Type | 已知问题 |
| 器件 | |
| IP | |