AR# 61018: Vivado Synthesis - Logics inserted between registers marked with ASYNC_REG
AR# 61018
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Vivado Synthesis - Logics inserted between registers marked with ASYNC_REG
描述
For registers with ASYNC_REG attributes, no optimizations should be done that might insert additional logic into the data path or increase the fanout of the associated registers.
However, in some cases logics can be inserted between registers with ASYNC_REG attributes.
解决方案
This is unexpected behavior and has been fixed in Vivado 2015.1.
To work around this issue, add a dont_touch attribute on the net between the two registers.